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1. general description the lpc4370 are arm cortex-m4 based microcontrollers for embedded applications which include an arm cortex-m0 coprocessor and an arm cortex-m0 subsystem for managing peripherals, 282 kb of sram, advanced configurable peripherals such as the state configurable timer (sct) and the serial general purpose i/o (sgpio) interface, two high-speed usb controllers, ethernet, lcd, an external memory controller, and multiple digital and analog peripherals including a high-speed 12-bit adc. the lpc4370 operate at cpu frequencies of up to 204 mhz. the arm cortex-m4 is a next generation 32-bit core that offers system enhancements such as low power consumption, enhanced de bug features, and a high level of support block integration. the arm cortex-m4 cpu incorporates a 3-stage pipeline, uses a harvard architecture with separa te local instruction and data buses as well as a third bus for peripherals, and includes an internal prefetch unit that supports speculative branching. the arm cortex-m4 supports single-cycle digital signal processing and simd instructions. a hardware floating-point processor is integrated in the core. the lpc4370 include an application arm cortex-m0 coprocessor and a second arm cortex-m0 subsystem for managing the sgpi o and spi peripherals. the arm cortex-m0 core is an energy-efficient and easy-to-use 32 -bit core which is c ode- and tool-compatible with the cortex-m4 core. both cortex-m0 cores offer up to 204 mhz performance with a simple instruction set and reduced code size. 2. features and benefits ? main cortex-m4 processor ? arm cortex-m4 processor, running at frequencies of up to 204 mhz. ? arm cortex-m4 built-in memory protection unit (mpu) supporting eight regions. ? arm cortex-m4 built-in nested vectored interrupt controller (nvic). ? hardware floatin g-point unit. ? non-maskable inte rrupt (nmi) input. ? jtag and serial wire debug (swd), serial trace, eight breakpoints, and four watch points. ? enhanced trace module (etm) and enhanced trace buffer (etb) support. ? system tick timer. ? cortex-m0 coprocessor ? arm cortex-m0 coprocessor capable of off-loading the main arm cortex-m4 processor. ? running at frequencies of up to 204 mhz. lpc4370 32-bit arm cortex-m4 + 2 x m0 mcu; 282 kb sram; ethernet; two hs usbs; 80 msps 12-bit adc; configurabl e peripherals rev. 2 ? 21 october 2013 product data sheet
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 2 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller ? jtag and built-in nvic. ? cortex-m0 subsystem ? arm cortex-m0 processor controlling the spi and sgpio peripher als residing on a separate ahb multilayer ma trix with direct access to 2 kb + 16 kb of sram. ? running at frequencies of up to 204 mhz. ? connected via a core-to-core bridge to the main ahb multilayer matrix and the main arm cortex-m4 processor. ? jtag and built-in nvic. ? on-chip memory ? 264 kb sram for code and data use on the main ahb multilayer matrix plus 18 kb of sram on the cortex-m0 subsystem. ? multiple sram blocks with separate bus access. two sram blocks can be powered down individually. ? 64 kb rom containing boot code and on-chip software drivers. ? 64-bit + 256 bit general-purpose one-time programmable (otp) memory. ? configurable digital peripherals ? serial gpio (sgpio) interface. ? state configurable timer (sct) subsystem on ahb. ? global input multiplexer arra y (gima) allows to cross-connect multiple inputs and outputs to event driven peripherals like the timers, sct, and adc0/1. ? serial interfaces ? quad spi flash interface (spifi) with fo ur lanes and up to 52 mb per second. ? 10/100t ethernet mac with rmii and mi i interfaces and dma support for high throughput at low cpu load . support for ieee 1588 time stamping/advanced time stamping (ieee 1588-2008 v2). ? one high-speed usb 2.0 ho st/device/otg interface with dma support and on-chip high-speed phy. ? one high-speed usb 2.0 host/device in terface with dma support, on-chip full-speed phy and ulpi interface to external high-speed phy. ? usb interface electrical test soft ware included in rom usb stack. ? one 550 uart with dma support and full modem interface. ? three 550 usarts with dma and synchronous mode support and a smart card interface conforming to is o7816 specification. one u sart with irda interface. ? two c_can 2.0b controllers with one ch annel each. use of c_can controller excludes operation of all other peripherals connected to the same bus bridge. see figure 1 and ref. 1 . ? two ssp controllers with fifo and multi-protocol supp ort. both ssps with dma support. ? one spi controller. ? one fast-mode plus i 2 c-bus interface with monitor mode and with open-drain i/o pins conforming to the full i 2 c-bus specification. supports data rates of up to 1mbit/s. ? one standard i 2 c-bus interface with monitor mode and with standard i/o pins. ? two i 2 s interfaces, each with dma support and with one input and one output. ? digital peripherals ? external memory controller (emc) supporting external sram, rom, nor flash, and sdram devices.
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 3 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller ? lcd controller with dma support and a programmable display resolution of up to 1024 h ? 768 v. supports monochrome and color stn panels and tft color panels; supports 1/2/4/8 bpp color look-up table (clut) and 16/24-bit direct pixel mapping. ? secure digital in put output (sd/mmc) card interface. ? eight-channel general-purpose dma (gpdma) controller can access all memories on the ahb and all dma-capable ahb slaves. ? 164 general-purpose input/output (gpio) pins with configur able pull-up/pull-down resistors and open-drain mode. ? gpio registers are located on the ahb fo r fast access. gpio ports have dma support. ? up to eight gpio pins can be selected from all gpio pins as edge and level sensitive interrupt sources. ? two gpio group interrupt modules enable an interrupt based on a programmable pattern of input states of a group of gpio pins. ? four general-pu rpose timer/counters with ca pture and match capabilities. ? one motor control pulse width modulator (pwm) for three-phase motor control. ? one quadrature encoder interface (qei). ? repetitive interrup t timer (ri timer). ? windowed watchdog timer (wwdt). ? ultra-low power real-time clock (rtc) on separate power domain with 256 bytes of battery powered backup registers. ? alarm timer; can be battery powered. ? analog peripherals ? one 10-bit dac with dma support and a data conversion rate of 400 ksamples/s. lbga256 package only. ? two 8-channel, 10-bit adcs (adc0/1) with dma support and a data conversion rate of 400 ksamples/s for a total of 16 independent channels. the 10-bit adcs are only available on the lbga256 package. ? one 6-channel, 12-bit high-speed adc (adchs) with dma support and a data conversion rate of 80 msamples/s. ? unique id for each device. ? clock generation unit ? crystal oscillator with an operating range of 1 mhz to 25 mhz. ? 12 mhz internal rc (irc) osc illator trimmed to 1 % accura cy over temperature and voltage. ? ultra-low power real-time clock (rtc) crystal oscillator. ? three plls allow cpu operation up to the maximum cpu rate without the need for a high-frequency crystal. the second pll is dedicated to the high-speed usb, the third pll can be used as audio pll. ? clock output. ? power ? single 3.3 v (2.2 v to 3.6 v) power supply with on-chip dc-to-dc converter for the core supply and the rtc power domain. ? rtc power domain can be powered separately by a 3 v battery supply. ? four reduced power modes: sleep, deep-sleep, power-down, and deep power-down.
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 4 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller ? processor wake-up from sleep mode via wake-up interrupts from various peripherals. ? wake-up from deep-sleep, power-down, and deep power-down modes via external interrupts and interrupts generated by battery powered blocks in the rtc power domain. ? brownout detect with four separate thre sholds for interrup t and forced reset. ? power-on reset (por). ? available as lbga256 and tfbga100 packages. 3. applications ? motor control ? embedded audio applications ? power management ? industrial automation ? white goods ? e-metering ? rfid readers
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 5 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller 4. ordering information 4.1 ordering options table 1. ordering information type number package name description version lpc4370fet256 lbga256 plastic low profile ball grid array package; 256 balls; body 17 ? 17 ? 1 mm sot740-2 LPC4370FET100 tfbga100 plastic thin fine-pitch ball grid array package; 100 balls; body 9 ? 9 ? 0.7 mm sot926-1 table 2. ordering options type number total sram lcd ethernet usb0 (host, device, otg) usb1 (host, device)/ ulpi interface 10-bit adc channels adc0/adc1 12-bit adc channels pwm qei gpio package lpc4370fet256 282 kb yes yes yes yes/yes 8/8 6 yes yes 164 lbga256 LPC4370FET100 282 kb no yes yes yes/no n/a 3 no no 49 tfbga100
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 6 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller 5. block diagram (1) not available on all parts (see ta b l e 2 ). fig 1. lpc4370 block diagram arm cortex-m4 test/debug interface i-code bus d-code bus system bus dma lcd (1) sd/ mmc ethernet 10/100 mac ieee 1588 high-speed usb0 host/ device/otg high-speed usb1 host/device emc high-speed phy 32 kb ahb sram 16 +16 kb ahb sram spifi 12-bit adc (adchs) hs gpio sct 64 kb rom i 2 c0 i 2 s0 i 2 s1 c_can1 motor control pwm timer3 timer2 usart2 usart3 ssp1 ri timer qei gima bridge 0 bridge 1 bridge 2 bridge 3 bridge ahb multilayer matrix lpc4370 128 kb local sram 72 kb local sram 10-bit adc0 10-bit adc1 c_can0 i 2 c1 10-bit dac bridge rgu ccu2 cgu ccu1 alarm timer configuration registers otp memory event router power mode control 12 mhz irc rtc power domain backup registers rtc osc rtc 002aag606 slaves arm cortex-m0 test/debug interface = connected to gpdma gpio interrupts gpio group0 interrupt gpio group1 interrupt wwdt usart0 uart1 ssp0 timer0 timer1 scu core-core bridge spi sgpio subsystem ahb multilayer matrix masters masters master arm cortex-m0 subsystem test/debug interface slaves 2 kb local sram 16 kb local sram system bus mpu fpu
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 7 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller 6. pinning information 6.1 pinning 6.2 pin description on the lpc4370, digital pins are grouped into 16 ports, named p0 to p9 and pa to pf, with up to 20 pins used per port. each digital pin can support up to eight different digital functions, including general purpose i/o (gpio), selectable through the system configuration unit (scu) regi sters. the pin name is not indicative of the gpio port assigned to it. not all functions listed in ta b l e 3 are available on all packages. see table 2 for availability of usb0, usb1, ethernet, and lcd functions. fig 2. pin configuration lbga256 package fig 3. pin configuration tfbga100 package 002aag607 lpc4370fet256 transparent top view t r p n m l j g k h f e d c b a 2 4 6 8 10 12 13 14 15 16 1357911 ball a1 index area 002aag608 LPC4370FET100 transparent top view j g k h f e d c b a 246810 13579 ball a1 index area
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 8 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller table 3. pin description lcd, ethernet, usb0, and usb1 functions are not available on all parts. see table 2 . symbol lbga256 tfbga100 reset state [2] type description multiplexed digital pins p0_0 l3 g2 [3] i; pu i/o gpio0[0] ? general purpose digital input/output pin. i/o ssp1_miso ? master in slave out for ssp1. i enet_rxd1 ? ethernet receive data 1 (rmii/mii interface). i/o sgpio0 ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. i/o i2s0_tx_ws ? transmit word select. it is driven by the master and received by the slave. corresponds to the signal ws in the i 2 s-bus specification . i/o i2s1_tx_ws ? transmit word select. it is driven by the master and received by the slave. corresponds to the signal ws in the i 2 s-bus specification . p0_1 m2 g1 [3] i; pu i/o gpio0[1] ? general purpose digital input/output pin. i/o ssp1_mosi ? master out slave in for ssp1. i enet_col ? ethernet collision detect (mii interface). i/o sgpio1 ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. enet_tx_en ? ethernet transmit enable (rmii/mii interface). i/o i2s1_tx_sda ? i2s1 transmit data. it is driven by the transmitter and read by the receiver. corresponds to the signal sd in the i 2 s-bus specification . p1_0 p2 h1 [3] i; pu i/o gpio0[4] ? general purpose digital input/output pin. i ctin_3 ? sct input 3. capture input 1 of timer 1. i/o emc_a5 ? external memory address line 5. - r ? function reserved. - r ? function reserved. i/o ssp0_ssel ? slave select for ssp0. i/o sgpio7 ? general purpose digital input/output pin. - r ? function reserved. p1_1 r2 k2 [3] i; pu i/o gpio0[8] ? general purpose digital input/output pin. boot pin (see ta b l e 5 ). o ctout_7 ? sct output 7. match output 3 of timer 1. i/o emc_a6 ? external memory address line 6. i/o sgpio8 ? general purpose digital input/output pin. - r ? function reserved. i/o ssp0_miso ? master in slave out for ssp0. - r ? function reserved. - r ? function reserved.
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 9 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller p1_2 r3 k1 [3] i; pu i/o gpio0[9] ? general purpose digital input/output pin. boot pin (see ta b l e 5 ). o ctout_6 ? sct output 6. match output 2 of timer 1. i/o emc_a7 ? external memory address line 7. i/o sgpio9 ? general purpose digital input/output pin. - r ? function reserved. i/o ssp0_mosi ? master out slave in for ssp0. - r ? function reserved. - r ? function reserved. p1_3 p5 j1 [3] i; pu i/o gpio0[10] ? general purpose digital input/output pin. o ctout_8 ? sct output 8. match output 0 of timer 2. i/o sgpio10 ? general purpose digital input/output pin. o emc_oe ? low active output enable signal. o usb0_ind1 ? usb0 port indicator led control output 1. i/o ssp1_miso ? master in slave out for ssp1. - r ? function reserved. o sd_rst ? sd/mmc reset signal for mmc4.4 card. p1_4 t3 j2 [3] i; pu i/o gpio0[11] ? general purpose digital input/output pin. o ctout_9 ? sct output 9. match output 1 of timer 2. i/o sgpio11 ? general purpose digital input/output pin. o emc_bls0 ? low active byte lane select signal 0. o usb0_ind0 ? usb0 port indicator led control output 0. i/o ssp1_mosi ? master out slave in for ssp1. - r ? function reserved. o sd_volt1 ? sd/mmc bus voltage select output 1. p1_5 r5 j4 [3] i; pu i/o gpio1[8] ? general purpose digital input/output pin. o ctout_10 ? sct output 10. match output 2 of timer 2. - r ? function reserved. o emc_cs0 ? low active chip select 0 signal. i usb0_pwr_fault ? port power fault signal indicating overcurrent condition; this signal monitors over-curr ent on the usb bus (external circuitry required to detect over-current condition). i/o ssp1_ssel ? slave select for ssp1. i/o sgpio15 ? general purpose digital input/output pin. o sd_pow ? sd/mmc power monitor output. table 3. pin description ?continued lcd, ethernet, usb0, and usb1 functions are not available on all parts. see table 2 . symbol lbga256 tfbga100 reset state [2] type description
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 10 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller p1_6 t4 k4 [3] i; pu i/o gpio1[9] ? general purpose digital input/output pin. i ctin_5 ? sct input 5. capture input 2 of timer 2. - r ? function reserved. o emc_we ? low active write enable signal. - r ? function reserved. - r ? function reserved. i/o sgpio14 ? general purpose digital input/output pin. i/o sd_cmd ? sd/mmc command signal. p1_7 t5 g4 [3] i; pu i/o gpio1[0] ? general purpose digital input/output pin. i u1_dsr ? data set ready input for uart1. o ctout_13 ? sct output 13. match output 1 of timer 3. i/o emc_d0 ? external memory data line 0. o usb0_ppwr ? vbus drive signal (towards external charge pump or power management unit); indicates that vbus must be driven (active high). add a pull-down resistor to disable the power switch at reset. this signal has opposite polarity compared to the usb_ppwr used on other nxp lpc parts. - r ? function reserved. - r ? function reserved. - r ? function reserved. p1_8 r7 h5 [3] i; pu i/o gpio1[1] ? general purpose digital input/output pin. o u1_dtr ? data terminal ready output for uart1. o ctout_12 ? sct output 12. match output 0 of timer 3. i/o emc_d1 ? external memory data line 1. - r ? function reserved. - r ? function reserved. - r ? function reserved. o sd_volt0 ? sd/mmc bus voltage select output 0. p1_9 t7 j5 [3] i; pu i/o gpio1[2] ? general purpose digital input/output pin. o u1_rts ? request to send output for uart1. o ctout_11 ? sct output 11. match output 3 of timer 2. i/o emc_d2 ? external memory data line 2. - r ? function reserved. - r ? function reserved. - r ? function reserved. i/o sd_dat0 ? sd/mmc data bus line 0. table 3. pin description ?continued lcd, ethernet, usb0, and usb1 functions are not available on all parts. see table 2 . symbol lbga256 tfbga100 reset state [2] type description
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 11 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller p1_10 r8 h6 [3] i; pu i/o gpio1[3] ? general purpose digital input/output pin. i u1_ri ? ring indicator input for uart1. o ctout_14 ? sct output 14. match output 2 of timer 3. i/o emc_d3 ? external memory data line 3. - r ? function reserved. - r ? function reserved. - r ? function reserved. i/o sd_dat1 ? sd/mmc data bus line 1. p1_11 t9 j7 [3] i; pu i/o gpio1[4] ? general purpose digital input/output pin. i u1_cts ? clear to send input for uart1. o ctout_15 ? sct output 15. match output 3 of timer 3. i/o emc_d4 ? external memory data line 4. - r ? function reserved. - r ? function reserved. - r ? function reserved. i/o sd_dat2 ? sd/mmc data bus line 2. p1_12 r9 k7 [3] i; pu i/o gpio1[5] ? general purpose digital input/output pin. i u1_dcd ? data carrier detect input for uart1. - r ? function reserved. i/o emc_d5 ? external memory data line 5. i t0_cap1 ? capture input 1 of timer 0. - r ? function reserved. i/o sgpio8 ? general purpose digital input/output pin. i/o sd_dat3 ? sd/mmc data bus line 3. p1_13 r10 h8 [3] i; pu i/o gpio1[6] ? general purpose digital input/output pin. o u1_txd ? transmitter output for uart1. - r ? function reserved. i/o emc_d6 ? external memory data line 6. i t0_cap0 ? capture input 0 of timer 0. - r ? function reserved. i/o sgpio9 ? general purpose digital input/output pin. i sd_cd ? sd/mmc card detect input. table 3. pin description ?continued lcd, ethernet, usb0, and usb1 functions are not available on all parts. see table 2 . symbol lbga256 tfbga100 reset state [2] type description
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 12 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller p1_14 r11 j8 [3] i; pu i/o gpio1[7] ? general purpose digital input/output pin. i u1_rxd ? receiver input for uart1. - r ? function reserved. i/o emc_d7 ? external memory data line 7. o t0_mat2 ? match output 2 of timer 0. - r ? function reserved. i/o sgpio10 ? general purpose digital input/output pin. - r ? function reserved. p1_15 t12 k8 [3] i; pu i/o gpio0[2] ? general purpose digital input/output pin. o u2_txd ? transmitter output for usart2. i/o sgpio2 ? general purpose digital input/output pin. i enet_rxd0 ? ethernet receive data 0 (rmii/mii interface). o t0_mat1 ? match output 1 of timer 0. - r ? function reserved. - r ? function reserved. - r ? function reserved. p1_16 m7 h9 [3] i; pu i/o gpio0[3] ? general purpose digital input/output pin. i u2_rxd ? receiver input for usart2. i/o sgpio3 ? general purpose digital input/output pin. i enet_crs ? ethernet carrier sense (mii interface). o t0_mat0 ? match output 0 of timer 0. - r ? function reserved. - r ? function reserved. i enet_rx_dv ? ethernet receive data valid (rmii/mii interface). p1_17 m8 h10 [4] i; pu i/o gpio0[12] ? general purpose digital input/output pin. i/o u2_uclk ? serial clock input/output for usart2 in synchronous mode. - r ? function reserved. i/o enet_mdio ? ethernet miim data input and output. i t0_cap3 ? capture input 3 of timer 0. o can1_td ? can1 transmitter output. i/o sgpio11 ? general purpose digital input/output pin. - r ? function reserved. table 3. pin description ?continued lcd, ethernet, usb0, and usb1 functions are not available on all parts. see table 2 . symbol lbga256 tfbga100 reset state [2] type description
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 13 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller p1_18 n12 j10 [3] i; pu i/o gpio0[13] ? general purpose digital input/output pin. i/o u2_dir ? rs-485/eia-485 output enable/direction control for usart2. - r ? function reserved. o enet_txd0 ? ethernet transmit data 0 (rmii/mii interface). o t0_mat3 ? match output 3 of timer 0. i can1_rd ? can1 receiver input. i/o sgpio12 ? general purpose digital input/output pin. - r ? function reserved. p1_19 m11 k9 [3] i; pu i enet_tx_clk (enet_ref_clk) ? ethernet transmit clock (mii interface) or ethernet refe rence clock (rmii interface). i/o ssp1_sck ? serial clock for ssp1. - r ? function reserved. - r ? function reserved. o clkout ? clock output pin. - r ? function reserved. o i2s0_rx_mclk ? i2s receive master clock. i/o i2s1_tx_sck ? transmit clock. it is driven by the master and received by the slave. corresponds to the signal sck in the i 2 s-bus specification. p1_20 m10 k10 [3] i; pu i/o gpio0[15] ? general purpose digital input/output pin. i/o ssp1_ssel ? slave select for ssp1. - r ? function reserved. o enet_txd1 ? ethernet transmit data 1 (rmii/mii interface). i t0_cap2 ? capture input 2 of timer 0. - r ? function reserved. i/o sgpio13 ? general purpose digital input/output pin. - r ? function reserved. p2_0 t16 g10 [3] i; pu i/o sgpio4 ? general purpose digital input/output pin. o u0_txd ? transmitter output for usart0. i/o emc_a13 ? external memory address line 13. o usb0_ppwr ? vbus drive signal (towards external charge pump or power management unit); indicates that vbus must be driven (active high). add a pull-down resistor to disable the power switch at reset. this signal has opposite polarity compared to the usb_ppwr used on other nxp lpc parts. i/o gpio5[0] ? general purpose digital input/output pin. - r ? function reserved. i t3_cap0 ? capture input 0 of timer 3. o enet_mdc ? ethernet miim clock. table 3. pin description ?continued lcd, ethernet, usb0, and usb1 functions are not available on all parts. see table 2 . symbol lbga256 tfbga100 reset state [2] type description
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 14 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller p2_1 n15 g7 [3] i; pu i/o sgpio5 ? general purpose digital input/output pin. i u0_rxd ? receiver input for usart0. i/o emc_a12 ? external memory address line 12. i usb0_pwr_fault ? port power fault signal indicating overcurrent condition; this signal monitors over-curr ent on the usb bus (external circuitry required to detect over-current condition). i/o gpio5[1] ? general purpose digital input/output pin. - r ? function reserved. i t3_cap1 ? capture input 1 of timer 3. - r ? function reserved. p2_2 m15 f5 [3] i; pu i/o sgpio6 ? general purpose digital input/output pin. i/o u0_uclk ? serial clock input/output for usart0 in synchronous mode. i/o emc_a11 ? external memory address line 11. o usb0_ind1 ? usb0 port indicator led control output 1. i/o gpio5[2] ? general purpose digital input/output pin. i ctin_6 ? sct input 6. capture input 1 of timer 3. i t3_cap2 ? capture input 2 of timer 3. - r ? function reserved. p2_3 j12 d8 [4] i; pu i/o sgpio12 ? general purpose digital input/output pin. i/o i2c1_sda ? i 2 c1 data input/output (this pin does not use a specialized i 2 c pad). o u3_txd ? transmitter output for usart3. i ctin_1 ? sct input 1. capture input 1 of timer 0. capture input 1 of timer 2. i/o gpio5[3] ? general purpose digital input/output pin. - r ? function reserved. o t3_mat0 ? match output 0 of timer 3. i usb0_pwr_en ? vbus drive signal (towards external charge pump or power management unit); indicates that vbus must be driven (active high). p2_4 k11 d9 [4] i; pu i/o sgpio13 ? general purpose digital input/output pin. i/o i2c1_scl ? i 2 c1 clock input/output (this pin does not use a specialized i 2 c pad). i u3_rxd ? receiver input for usart3. i ctin_0 ? sct input 0. capture input 0 of timer 0, 1, 2, 3. i/o gpio5[4] ? general purpose digital input/output pin. - r ? function reserved. o t3_mat1 ? match output 1 of timer 3. i usb0_pwr_fault ? port power fault signal indicating overcurrent condition; this signal monitors over-curr ent on the usb bus (external circuitry required to detect over-current condition). table 3. pin description ?continued lcd, ethernet, usb0, and usb1 functions are not available on all parts. see table 2 . symbol lbga256 tfbga100 reset state [2] type description
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 15 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller p2_5 k14 d10 [4] i; pu i/o sgpio14 ? general purpose digital input/output pin. i ctin_2 ? sct input 2. capture input 2 of timer 0. i usb1_vbus ? monitors the presence of usb1 bus power. note: this signal must be high for usb reset to occur. i adctrig1 ? adc trigger input 1. i/o gpio5[5] ? general purpose digital input/output pin. - r ? function reserved. o t3_mat2 ? match output 2 of timer 3. o usb0_ind0 ? usb0 port indicator led control output 0. p2_6 k16 g9 [3] i; pu i/o sgpio7 ? general purpose digital input/output pin. i/o u0_dir ? rs-485/eia-485 output enable/direction control for usart0. i/o emc_a10 ? external memory address line 10. o usb0_ind0 ? usb0 port indicator led control output 0. i/o gpio5[6] ? general purpose digital input/output pin. i ctin_7 ? sct input 7. i t3_cap3 ? capture input 3 of timer 3. - r ? function reserved. p2_7 h14 c10 [3] i; pu i/o gpio0[7] ? general purpose digital input/output pin. if this pin is pulled low at reset, the part enters isp mode using usart0. o ctout_1 ? sct output 1. match output 1 of timer 0. i/o u3_uclk ? serial clock input/output for usart3 in synchronous mode. i/o emc_a9 ? external memory address line 9. - r ? function reserved. - r ? function reserved. o t3_mat3 ? match output 3 of timer 3. - r ? function reserved. p2_8 j16 c6 [3] i; pu i/o sgpio15 ? general purpose digital input/output pin. boot pin (see ta b l e 5 ). o ctout_0 ? sct output 0. match output 0 of timer 0. i/o u3_dir ? rs-485/eia-485 output enable/direction control for usart3. i/o emc_a8 ? external memory address line 8. i/o gpio5[7] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. - r ? function reserved. table 3. pin description ?continued lcd, ethernet, usb0, and usb1 functions are not available on all parts. see table 2 . symbol lbga256 tfbga100 reset state [2] type description
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 16 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller p2_9 h16 b10 [3] i; pu i/o gpio1[10] ? general purpose digital inpu t/output pin. boot pin (see table 5 ). o ctout_3 ? sct output 3. match output 3 of timer 0. i/o u3_baud ? baud pin for usart3. i/o emc_a0 ? external memory address line 0. - r ? function reserved. - r ? function reserved. - r ? function reserved. - r ? function reserved. p2_10 g16 e8 [3] i; pu i/o gpio0[14] ? general purpose digital input/output pin. o ctout_2 ? sct output 2. match output 2 of timer 0. o u2_txd ? transmitter output for usart2. i/o emc_a1 ? external memory address line 1. - r ? function reserved. - r ? function reserved. - r ? function reserved. - r ? function reserved. p2_11 f16 a9 [3] i; pu i/o gpio1[11] ? general purpose digital input/output pin. o ctout_5 ? sct output 5. match output 1 of timer 1. i u2_rxd ? receiver input for usart2. i/o emc_a2 ? external memory address line 2. - r ? function reserved. - r ? function reserved. - r ? function reserved. - r ? function reserved. p2_12 e15 b9 [3] i; pu i/o gpio1[12] ? general purpose digital input/output pin. o ctout_4 ? sct output 4. match output 0 of timer 1. - r ? function reserved. i/o emc_a3 ? external memory address line 3. - r ? function reserved. - r ? function reserved. - r ? function reserved. i/o u2_uclk ? serial clock input/output for usart2 in synchronous mode. table 3. pin description ?continued lcd, ethernet, usb0, and usb1 functions are not available on all parts. see table 2 . symbol lbga256 tfbga100 reset state [2] type description
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 17 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller p2_13 c16 a10 [3] i; pu i/o gpio1[13] ? general purpose digital input/output pin. i ctin_4 ? sct input 4. capture input 2 of timer 1. - r ? function reserved. i/o emc_a4 ? external memory address line 4. - r ? function reserved. - r ? function reserved. - r ? function reserved. i/o u2_dir ? rs-485/eia-485 output enable/direction control for usart2. p3_0 f13 a8 [3] i; pu i/o i2s0_rx_sck ? i2s receive clock. it is driven by the master and received by the slave. corresponds to the signal sck in the i 2 s-bus specification . o i2s0_rx_mclk ? i2s receive master clock. i/o i2s0_tx_sck ? transmit clock. it is driven by the master and received by the slave. corresponds to the signal sck in the i 2 s-bus specification. o i2s0_tx_mclk ? i2s transmit master clock. i/o ssp0_sck ? serial clock for ssp0. - r ? function reserved. - r ? function reserved. - r ? function reserved. p3_1 g11 f7 [3] i; pu i/o i2s0_tx_ws ? transmit word select. it is driven by the master and received by the slave. corresponds to the signal ws in the i 2 s-bus specification . i/o i2s0_rx_ws ? receive word select. it is driven by the master and received by the slave. corresponds to the signal ws in the i 2 s-bus specification . i can0_rd ? can receiver input. o usb1_ind1 ? usb1 port indicator led control output 1. i/o gpio5[8] ? general purpose digital input/output pin. - r ? function reserved. o lcd_vd15 ? lcd data. - r ? function reserved. p3_2 f11 g6 [3] i; pu i/o i2s0_tx_sda ? i2s transmit data. it is driven by the transmitter and read by the receiver. corresponds to the signal sd in the i 2 s-bus specification . i/o i2s0_rx_sda ? i2s receive data. it is driven by the transmitter and read by the receiver. corresponds to the signal sd in the i 2 s-bus specification . o can0_td ? can transmitter output. o usb1_ind0 ? usb1 port indicator led control output 0. i/o gpio5[9] ? general purpose digital input/output pin. - r ? function reserved. o lcd_vd14 ? lcd data. - r ? function reserved. table 3. pin description ?continued lcd, ethernet, usb0, and usb1 functions are not available on all parts. see table 2 . symbol lbga256 tfbga100 reset state [2] type description
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 18 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller p3_3 b14 a7 [5] i; pu - r ? function reserved. i/o spi_sck ? serial clock for spi. i/o ssp0_sck ? serial clock for ssp0. o spifi_sck ? serial clock for spifi. o cgu_out1 ? cgu spare clock output 1. - r ? function reserved. o i2s0_tx_mclk ? i2s transmit master clock. i/o i2s1_tx_sck ? transmit clock. it is driven by the master and received by the slave. corresponds to the signal sck in the i 2 s-bus specification. p3_4 a15 b8 [3] i; pu i/o gpio1[14] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. i/o spifi_sio3 ? i/o lane 3 for spifi. o u1_txd ? transmitter output for uart 1. i/o i2s0_tx_ws ? transmit word select. it is driven by the master and received by the slave. corresponds to the signal ws in the i 2 s-bus specification . i/o i2s1_rx_sda ? i2s1 receive data. it is driven by the transmitter and read by the receiver. corresponds to the signal sd in the i 2 s-bus specification . o lcd_vd13 ? lcd data. p3_5 c12 b7 [3] i; pu i/o gpio1[15] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. i/o spifi_sio2 ? i/o lane 2 for spifi. i u1_rxd ? receiver input for uart 1. i/o i2s0_tx_sda ? i2s transmit data. it is driven by the transmitter and read by the receiver. corresponds to the signal sd in the i 2 s-bus specification . i/o i2s1_rx_ws ? receive word select. it is driven by the master and received by the slave. corresponds to the signal ws in the i 2 s-bus specification . o lcd_vd12 ? lcd data. p3_6 b13 c7 [3] i; pu i/o gpio0[6] ? general purpose digital input/output pin. i/o spi_miso ? master in slave out for spi. i/o ssp0_ssel ? slave select for ssp0. i/o spifi_miso ? input 1 in spifi quad mo de; spifi out put io1. - r ? function reserved. i/o ssp0_miso ? master in slave out for ssp0. - r ? function reserved. - r ? function reserved. table 3. pin description ?continued lcd, ethernet, usb0, and usb1 functions are not available on all parts. see table 2 . symbol lbga256 tfbga100 reset state [2] type description
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 19 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller p3_7 c11 d7 [3] i; pu - r ? function reserved. i/o spi_mosi ? master out slave in for spi. i/o ssp0_miso ? master in slave out for ssp0. i/o spifi_mosi ? input i0 in spifi quad mode; spifi output io0. i/o gpio5[10] ? general purpose digital input/output pin. i/o ssp0_mosi ? master out slave in for ssp0. - r ? function reserved. - r ? function reserved. p3_8 c10 e7 [3] i; pu - r ? function reserved. i spi_ssel ? slave select for spi. note that this pin in an input pin only. the spi in master mode cannot drive t he cs input on the slave. any gpio pin can be used for spi chip select in master mode. i/o ssp0_mosi ? master out slave in for ssp0. i/o spifi_cs ? spifi serial flas h chip select. i/o gpio5[11] ? general purpose digital input/output pin. i/o ssp0_ssel ? slave select for ssp0. - r ? function reserved. - r ? function reserved. p4_0 d5 - [3] i; pu i/o gpio2[0] ? general purpose digital input/output pin. o mcoa0 ? motor control pwm channel 0, output a. i nmi ? external interrupt input to nmi. - r ? function reserved. - r ? function reserved. o lcd_vd13 ? lcd data. i/o u3_uclk ? serial clock input/output for usart3 in synchronous mode. - r ? function reserved. p4_1 a1 - [6] [13] i; pu i/o gpio2[1] ? general purpose digital input/output pin. o ctout_1 ? sct output 1. match output 1 of timer 0. o lcd_vd0 ? lcd data. - r ? function reserved. - r ? function reserved. o lcd_vd19 ? lcd data. o u3_txd ? transmitter output for usart3. i enet_col ? ethernet collision detect (mii interface). ai adc0_1 ? adc0, input channel 1. configure the pin as gpio input and use the adc function select register in the scu to select the adc. table 3. pin description ?continued lcd, ethernet, usb0, and usb1 functions are not available on all parts. see table 2 . symbol lbga256 tfbga100 reset state [2] type description
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 20 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller p4_2 d3 - [3] i; pu i/o gpio2[2] ? general purpose digital input/output pin. o ctout_0 ? sct output 0. match output 0 of timer 0. o lcd_vd3 ? lcd data. - r ? function reserved. - r ? function reserved. o lcd_vd12 ? lcd data. i u3_rxd ? receiver input for usart3. i/o sgpio8 ? general purpose digital input/output pin. p4_3 c2 - [6] [13] i; pu i/o gpio2[3] ? general purpose digital input/output pin. o ctout_3 ? sct output 3. match output 3 of timer 0. o lcd_vd2 ? lcd data. - r ? function reserved. - r ? function reserved. o lcd_vd21 ? lcd data. i/o u3_baud ? baud pin for usart3. i/o sgpio9 ? general purpose digital input/output pin. ai adc0_0 ? adc0, input channel 0. configure the pin as gpio input and use the adc function select register in the scu to select the adc. p4_4 b1 - [6] i; pu i/o gpio2[4] ? general purpose digital input/output pin. o ctout_2 ? sct output 2. match output 2 of timer 0. o lcd_vd1 ? lcd data. - r ? function reserved. - r ? function reserved. o lcd_vd20 ? lcd data. i/o u3_dir ? rs-485/eia-485 output enable/direction control for usart3. i/o sgpio10 ? general purpose digital input/output pin. o dac ? dac output. configure the pin as gpio input and use the analog function select register in the scu to select the dac. p4_5 d2 - [3] i; pu i/o gpio2[5] ? general purpose digital input/output pin. o ctout_5 ? sct output 5. match output 1 of timer 1. o lcd_fp ? frame pulse (stn). vertical synchronization pulse (tft). - r ? function reserved. - r ? function reserved. - r ? function reserved. - r ? function reserved. i/o sgpio11 ? general purpose digital input/output pin. table 3. pin description ?continued lcd, ethernet, usb0, and usb1 functions are not available on all parts. see table 2 . symbol lbga256 tfbga100 reset state [2] type description
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 21 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller p4_6 c1 - [3] i; pu i/o gpio2[6] ? general purpose digital input/output pin. o ctout_4 ? sct output 4. match output 0 of timer 1. o lcd_enab/lcdm ? stn ac bias drive or tft data enable input. - r ? function reserved. - r ? function reserved. - r ? function reserved. - r ? function reserved. i/o sgpio12 ? general purpose digital input/output pin. p4_7 h4 - [3] o; pu o lcd_dclk ? lcd panel clock. i gp_clkin ? general purpose clock input to the cgu. - r ? function reserved. - r ? function reserved. - r ? function reserved. - r ? function reserved. i/o i2s1_tx_sck ? transmit clock. it is driven by the master and received by the slave. corresponds to the signal sck in the i 2 s-bus specification. i/o i2s0_tx_sck ? transmit clock. it is driven by the master and received by the slave. corresponds to the signal sck in the i 2 s-bus specification. p4_8 e2 - [3] i; pu - r ? function reserved. i ctin_5 ? sct input 5. capture input 2 of timer 2. o lcd_vd9 ? lcd data. - r ? function reserved. i/o gpio5[12] ? general purpose digital input/output pin. o lcd_vd22 ? lcd data. o can1_td ? can1 transmitter output. i/o sgpio13 ? general purpose digital input/output pin. p4_9 l2 - [3] i; pu - r ? function reserved. i ctin_6 ? sct input 6. capture input 1 of timer 3. o lcd_vd11 ? lcd data. - r ? function reserved. i/o gpio5[13] ? general purpose digital input/output pin. o lcd_vd15 ? lcd data. i can1_rd ? can1 receiver input. i/o sgpio14 ? general purpose digital input/output pin. table 3. pin description ?continued lcd, ethernet, usb0, and usb1 functions are not available on all parts. see table 2 . symbol lbga256 tfbga100 reset state [2] type description
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 22 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller p4_10 m3 - [3] i; pu - r ? function reserved. i ctin_2 ? sct input 2. capture input 2 of timer 0. o lcd_vd10 ? lcd data. - r ? function reserved. i/o gpio5[14] ? general purpose digital input/output pin. o lcd_vd14 ? lcd data. - r ? function reserved. i/o sgpio15 ? general purpose digital input/output pin. p5_0 n3 - [3] i; pu i/o gpio2[9] ? general purpose digital input/output pin. o mcob2 ? motor control pwm channel 2, output b. i/o emc_d12 ? external memory data line 12. - r ? function reserved. i u1_dsr ? data set ready input for uart 1. i t1_cap0 ? capture input 0 of timer 1. - r ? function reserved. - r ? function reserved. p5_1 p3 - [3] i; pu i/o gpio2[10] ? general purpose digital input/output pin. i mci2 ? motor control pwm channel 2, input. i/o emc_d13 ? external memory data line 13. - r ? function reserved. o u1_dtr ? data terminal ready output for ua rt 1. can also be configured to be an rs-485/eia-485 output enable signal for uart 1. i t1_cap1 ? capture input 1 of timer 1. - r ? function reserved. - r ? function reserved. p5_2 r4 - [3] i; pu i/o gpio2[11] ? general purpose digital input/output pin. i mci1 ? motor control pwm channel 1, input. i/o emc_d14 ? external memory data line 14. - r ? function reserved. o u1_rts ? request to send output for uart 1. can also be configured to be an rs-485/eia-485 output enable signal for uart 1. i t1_cap2 ? capture input 2 of timer 1. - r ? function reserved. - r ? function reserved. table 3. pin description ?continued lcd, ethernet, usb0, and usb1 functions are not available on all parts. see table 2 . symbol lbga256 tfbga100 reset state [2] type description
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 23 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller p5_3 t8 - [3] i; pu i/o gpio2[12] ? general purpose digital input/output pin. i mci0 ? motor control pwm channel 0, input. i/o emc_d15 ? external memory data line 15. - r ? function reserved. i u1_ri ? ring indicator input for uart 1. i t1_cap3 ? capture input 3 of timer 1. - r ? function reserved. - r ? function reserved. p5_4 p9 - [3] i; pu i/o gpio2[13] ? general purpose digital input/output pin. o mcob0 ? motor control pwm channel 0, output b. i/o emc_d8 ? external memory data line 8. - r ? function reserved. i u1_cts ? clear to send input for uart 1. o t1_mat0 ? match output 0 of timer 1. - r ? function reserved. - r ? function reserved. p5_5 p10 - [3] i; pu i/o gpio2[14] ? general purpose digital input/output pin. o mcoa1 ? motor control pwm channel 1, output a. i/o emc_d9 ? external memory data line 9. - r ? function reserved. i u1_dcd ? data carrier detect input for uart 1. o t1_mat1 ? match output 1 of timer 1. - r ? function reserved. - r ? function reserved. p5_6 t13 - [3] i; pu i/o gpio2[15] ? general purpose digital input/output pin. o mcob1 ? motor control pwm channel 1, output b. i/o emc_d10 ? external memory data line 10. - r ? function reserved. o u1_txd ? transmitter output for uart 1. o t1_mat2 ? match output 2 of timer 1. - r ? function reserved. - r ? function reserved. table 3. pin description ?continued lcd, ethernet, usb0, and usb1 functions are not available on all parts. see table 2 . symbol lbga256 tfbga100 reset state [2] type description
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 24 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller p5_7 r12 - [3] i; pu i/o gpio2[7] ? general purpose digital input/output pin. o mcoa2 ? motor control pwm channel 2, output a. i/o emc_d11 ? external memory data line 11. - r ? function reserved. i u1_rxd ? receiver input for uart 1. o t1_mat3 ? match output 3 of timer 1. - r ? function reserved. - r ? function reserved. p6_0 m12 h7 [3] i; pu - r ? function reserved. o i2s0_rx_mclk ? i2s receive master clock. - r ? function reserved. - r ? function reserved. i/o i2s0_rx_sck ? receive clock. it is driven by the master and received by the slave. corresponds to the signal sck in the i 2 s-bus specification . - r ? function reserved. - r ? function reserved. - r ? function reserved. p6_1 r15 g5 [3] i; pu i/o gpio3[0] ? general purpose digital input/output pin. o emc_dycs1 ? sdram chip select 1. i/o u0_uclk ? serial clock input/output for usart0 in synchronous mode. i/o i2s0_rx_ws ? receive word select. it is driven by the master and received by the slave. corresponds to the signal ws in the i 2 s-bus specification . - r ? function reserved. i t2_cap0 ? capture input 2 of timer 2. - r ? function reserved. - r ? function reserved. p6_2 l13 j9 [3] i; pu i/o gpio3[1] ? general purpose digital input/output pin. o emc_ckeout1 ? sdram clock enable 1. i/o u0_dir ? rs-485/eia-485 output enable/direction control for usart0. i/o i2s0_rx_sda ? i2s receive data. it is driven by the transmitter and read by the receiver. corresponds to the signal sd in the i 2 s-bus specification . - r ? function reserved. i t2_cap1 ? capture input 1 of timer 2. - r ? function reserved. - r ? function reserved. table 3. pin description ?continued lcd, ethernet, usb0, and usb1 functions are not available on all parts. see table 2 . symbol lbga256 tfbga100 reset state [2] type description
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 25 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller p6_3 p15 - [3] i; pu i/o gpio3[2] ? general purpose digital input/output pin. i usb0_pwr_en ? vbus drive signal (towards external charge pump or power management unit); indicates that the vbus signal must be driven (active high). i/o sgpio4 ? general purpose digital input/output pin. o emc_cs1 ? low active chip select 1 signal. - r ? function reserved. i t2_cap2 ? capture input 2 of timer 2. - r ? function reserved. - r ? function reserved. p6_4 r16 f6 [3] i; pu i/o gpio3[3] ? general purpose digital input/output pin. i ctin_6 ? sct input 6. capture input 1 of timer 3. o u0_txd ? transmitter output for usart0. o emc_cas ? low active sdram column address strobe. - r ? function reserved. - r ? function reserved. - r ? function reserved. - r ? function reserved. p6_5 p16 f9 [3] i; pu i/o gpio3[4] ? general purpose digital input/output pin. o ctout_6 ? sct output 6. match output 2 of timer 1. i u0_rxd ? receiver input for usart0. o emc_ras ? low active sdram row address strobe. - r ? function reserved. - r ? function reserved. - r ? function reserved. - r ? function reserved. p6_6 l14 - [3] i; pu i/o gpio0[5] ? general purpose digital input/output pin. o emc_bls1 ? low active byte lane select signal 1. i/o sgpio5 ? general purpose digital input/output pin. i usb0_pwr_fault ? port power fault signal indicating overcurrent condition; this signal monitors over-curr ent on the usb bus (external circuitry required to detect over-current condition). - r ? function reserved. i t2_cap3 ? capture input 3 of timer 2. - r ? function reserved. - r ? function reserved. table 3. pin description ?continued lcd, ethernet, usb0, and usb1 functions are not available on all parts. see table 2 . symbol lbga256 tfbga100 reset state [2] type description
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 26 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller p6_7 j13 - [3] i; pu - r ? function reserved. i/o emc_a15 ? external memory address line 15. i/o sgpio6 ? general purpose digital input/output pin. o usb0_ind1 ? usb0 port indicator led control output 1. i/o gpio5[15] ? general purpose digital input/output pin. o t2_mat0 ? match output 0 of timer 2. - r ? function reserved. - r ? function reserved. p6_8 h13 - [3] i; pu - r ? function reserved. i/o emc_a14 ? external memory address line 14. i/o sgpio7 ? general purpose digital input/output pin. o usb0_ind0 ? usb0 port indicator led control output 0. i/o gpio5[16] ? general purpose digital input/output pin. o t2_mat1 ? match output 1 of timer 2. - r ? function reserved. - r ? function reserved. p6_9 j15 f8 [3] i; pu i/o gpio3[5] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. o emc_dycs0 ? sdram chip select 0. - r ? function reserved. o t2_mat2 ? match output 2 of timer 2. - r ? function reserved. - r ? function reserved. p6_10 h15 - [3] i; pu i/o gpio3[6] ? general purpose digital input/output pin. o mcabort ? motor control pwm, low-active fast abort. - r ? function reserved. o emc_dqmout1 ? data mask 1 used with sdram and static devices. - r ? function reserved. - r ? function reserved. - r ? function reserved. - r ? function reserved. table 3. pin description ?continued lcd, ethernet, usb0, and usb1 functions are not available on all parts. see table 2 . symbol lbga256 tfbga100 reset state [2] type description
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 27 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller p6_11 h12 c9 [3] i; pu i/o gpio3[7] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. o emc_ckeout0 ? sdram clock enable 0. - r ? function reserved. o t2_mat3 ? match output 3 of timer 2. - r ? function reserved. - r ? function reserved. p6_12 g15 - [3] i; pu i/o gpio2[8] ? general purpose digital input/output pin. o ctout_7 ? sct output 7. match output 3 of timer 1. - r ? function reserved. o emc_dqmout0 ? data mask 0 used with sdram and static devices. - r ? function reserved. - r ? function reserved. - r ? function reserved. - r ? function reserved. p7_0 b16 - [3] i; pu i/o gpio3[8] ? general purpose digital input/output pin. o ctout_14 ? sct output 14. match output 2 of timer 3. - r ? function reserved. o lcd_le ? line end signal. - r ? function reserved. - r ? function reserved. - r ? function reserved. i/o sgpio4 ? general purpose digital input/output pin. p7_1 c14 - [3] i; pu i/o gpio3[9] ? general purpose digital input/output pin. o ctout_15 ? sct output 15. match output 3 of timer 3. i/o i2s0_tx_ws ? transmit word select. it is driven by the master and received by the slave. corresponds to the signal ws in the i 2 s-bus specification . o lcd_vd19 ? lcd data. o lcd_vd7 ? lcd data. - r ? function reserved. o u2_txd ? transmitter output for usart2. i/o sgpio5 ? general purpose digital input/output pin. table 3. pin description ?continued lcd, ethernet, usb0, and usb1 functions are not available on all parts. see table 2 . symbol lbga256 tfbga100 reset state [2] type description
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 28 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller p7_2 a16 - [3] i; pu i/o gpio3[10] ? general purpose digital input/output pin. i ctin_4 ? sct input 4. capture input 2 of timer 1. i/o i2s0_tx_sda ? i2s transmit data. it is driven by the transmitter and read by the receiver. corresponds to the signal sd in the i 2 s-bus specification . o lcd_vd18 ? lcd data. o lcd_vd6 ? lcd data. - r ? function reserved. i u2_rxd ? receiver input for usart2. i/o sgpio6 ? general purpose digital input/output pin. p7_3 c13 - [3] i; pu i/o gpio3[11] ? general purpose digital input/output pin. i ctin_3 ? sct input 3. capture input 1 of timer 1. - r ? function reserved. o lcd_vd17 ? lcd data. o lcd_vd5 ? lcd data. - r ? function reserved. - r ? function reserved. - r ? function reserved. p7_4 c8 - [6] i; pu i/o gpio3[12] ? general purpose digital input/output pin. o ctout_13 ? sct output 13. match output 1 of timer 3. - r ? function reserved. o lcd_vd16 ? lcd data. o lcd_vd4 ? lcd data. o tracedata[0] ? trace data, bit 0. - r ? function reserved. - r ? function reserved. ai adc0_4 ? adc0, input channel 4. configure the pin as gpio input and use the adc function select register in the scu to select the adc. p7_5 a7 - [6] i; pu i/o gpio3[13] ? general purpose digital input/output pin. o ctout_12 ? sct output 12. match output 0 of timer 3. - r ? function reserved. o lcd_vd8 ? lcd data. o lcd_vd23 ? lcd data. o tracedata[1] ? trace data, bit 1. - r ? function reserved. - r ? function reserved. ai adc0_3 ? adc0, input channel 3. configure the pin as gpio input and use the adc function select register in the scu to select the adc. table 3. pin description ?continued lcd, ethernet, usb0, and usb1 functions are not available on all parts. see table 2 . symbol lbga256 tfbga100 reset state [2] type description
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 29 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller p7_6 c7 - [3] i; pu i/o gpio3[14] ? general purpose digital input/output pin. o ctout_11 ? sct output 1. match output 3 of timer 2. - r ? function reserved. o lcd_lp ? line synchronization pulse (stn). horizontal synchronization pulse (tft). - r ? function reserved. o tracedata[2] ? trace data, bit 2. - r ? function reserved. - r ? function reserved. p7_7 b6 - [6] [13] i; pu i/o gpio3[15] ? general purpose digital input/output pin. o ctout_8 ? sct output 8. match output 0 of timer 2. - r ? function reserved. o lcd_pwr ? lcd panel power enable. - r ? function reserved. o tracedata[3] ? trace data, bit 3. o enet_mdc ? ethernet miim clock. i/o sgpio7 ? general purpose digital input/output pin. ai adc1_6 ? adc1, input channel 6. configure the pin as gpio input and use the adc function select register in the scu to select the adc. p8_0 e5 - [4] [13] i; pu i/o gpio4[0] ? general purpose digital input/output pin. i usb0_pwr_fault ? port power fault signal indicating overcurrent condition; this signal monitors over-curr ent on the usb bus (external circuitry required to detect over-current condition). - r ? function reserved. i mci2 ? motor control pwm channel 2, input. i/o sgpio8 ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. o t0_mat0 ? match output 0 of timer 0. p8_1 h5 - [4] i; pu i/o gpio4[1] ? general purpose digital input/output pin. o usb0_ind1 ? usb0 port indicator led control output 1. - r ? function reserved. i mci1 ? motor control pwm channel 1, input. i/o sgpio9 ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. o t0_mat1 ? match output 1 of timer 0. table 3. pin description ?continued lcd, ethernet, usb0, and usb1 functions are not available on all parts. see table 2 . symbol lbga256 tfbga100 reset state [2] type description
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 30 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller p8_2 k4 - [4] i; pu i/o gpio4[2] ? general purpose digital input/output pin. o usb0_ind0 ? usb0 port indicator led control output 0. - r ? function reserved. i mci0 ? motor control pwm channel 0, input. i/o sgpio10 ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. o t0_mat2 ? match output 2 of timer 0. p8_3 j3 - [3] i; pu i/o gpio4[3] ? general purpose digital input/output pin. i/o usb1_ulpi_d2 ? ulpi link bidirectional data line 2. - r ? function reserved. o lcd_vd12 ? lcd data. o lcd_vd19 ? lcd data. - r ? function reserved. - r ? function reserved. o t0_mat3 ? match output 3 of timer 0. p8_4 j2 - [3] i; pu i/o gpio4[4] ? general purpose digital input/output pin. i/o usb1_ulpi_d1 ? ulpi link bidirectional data line 1. - r ? function reserved. o lcd_vd7 ? lcd data. o lcd_vd16 ? lcd data. - r ? function reserved. - r ? function reserved. i t0_cap0 ? capture input 0 of timer 0. p8_5 j1 - [3] i; pu i/o gpio4[5] ? general purpose digital input/output pin. i/o usb1_ulpi_d0 ? ulpi link bidirectional data line 0. - r ? function reserved. o lcd_vd6 ? lcd data. o lcd_vd8 ? lcd data. - r ? function reserved. - r ? function reserved. i t0_cap1 ? capture input 1 of timer 0. table 3. pin description ?continued lcd, ethernet, usb0, and usb1 functions are not available on all parts. see table 2 . symbol lbga256 tfbga100 reset state [2] type description
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 31 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller p8_6 k3 - [3] i; pu i/o gpio4[6] ? general purpose digital input/output pin. i usb1_ulpi_nxt ? ulpi link nxt signal. data flow control signal from the phy. - r ? function reserved. o lcd_vd5 ? lcd data. o lcd_lp ? line synchronization pulse (stn). horizontal synchronization pulse (tft). - r ? function reserved. - r ? function reserved. i t0_cap2 ? capture input 2 of timer 0. p8_7 k1 - [3] i; pu i/o gpio4[7] ? general purpose digital input/output pin. o usb1_ulpi_stp ? ulpi link stp signal. asserted to end or interrupt transfers to the phy. - r ? function reserved. o lcd_vd4 ? lcd data. o lcd_pwr ? lcd panel power enable. - r ? function reserved. - r ? function reserved. i t0_cap3 ? capture input 3 of timer 0. p8_8 l1 - [3] i; pu - r ? function reserved. i usb1_ulpi_clk ? ulpi link clk signal. 60 mhz clock generated by the phy. - r ? function reserved. - r ? function reserved. - r ? function reserved. - r ? function reserved. o cgu_out0 ? cgu spare clock output 0. o i2s1_tx_mclk ? i2s1 transmit master clock. p9_0 t1 - [3] i; pu i/o gpio4[12] ? general purpose digital input/output pin. o mcabort ? motor control pwm, low-active fast abort. - r ? function reserved. - r ? function reserved. - r ? function reserved. i enet_crs ? ethernet carrier sense (mii interface). i/o sgpio0 ? general purpose digital input/output pin. i/o ssp0_ssel ? slave select for ssp0. table 3. pin description ?continued lcd, ethernet, usb0, and usb1 functions are not available on all parts. see table 2 . symbol lbga256 tfbga100 reset state [2] type description
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 32 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller p9_1 n6 - [3] i; pu i/o gpio4[13] ? general purpose digital input/output pin. o mcoa2 ? motor control pwm channel 2, output a. - r ? function reserved. - r ? function reserved. i/o i2s0_tx_ws ? transmit word select. it is driven by the master and received by the slave. corresponds to the signal ws in the i 2 s-bus specification . i enet_rx_er ? ethernet receive error (mii interface). i/o sgpio1 ? general purpose digital input/output pin. i/o ssp0_miso ? master in slave out for ssp0. p9_2 n8 - [3] i; pu i/o gpio4[14] ? general purpose digital input/output pin. o mcob2 ? motor control pwm channel 2, output b. - r ? function reserved. - r ? function reserved. i/o i2s0_tx_sda ? i2s transmit data. it is driven by the transmitter and read by the receiver. corresponds to the signal sd in the i 2 s-bus specification . i enet_rxd3 ? ethernet receive data 3 (mii interface). i/o sgpio2 ? general purpose digital input/output pin. i/o ssp0_mosi ? master out slave in for ssp0. p9_3 m6 - [3] i; pu i/o gpio4[15] ? general purpose digital input/output pin. o mcoa0 ? motor control pwm channel 0, output a. o usb1_ind1 ? usb1 port indicator led control output 1. - r ? function reserved. - r ? function reserved. i enet_rxd2 ? ethernet receive data 2 (mii interface). i/o sgpio9 ? general purpose digital input/output pin. o u3_txd ? transmitter output for usart3. p9_4 n10 - [3] i; pu - r ? function reserved. o mcob0 ? motor control pwm channel 0, output b. o usb1_ind0 ? usb1 port indicator led control output 0. - r ? function reserved. i/o gpio5[17] ? general purpose digital input/output pin. o enet_txd2 ? ethernet transmit data 2 (mii interface). i/o sgpio4 ? general purpose digital input/output pin. i u3_rxd ? receiver input for usart3. table 3. pin description ?continued lcd, ethernet, usb0, and usb1 functions are not available on all parts. see table 2 . symbol lbga256 tfbga100 reset state [2] type description
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 33 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller p9_5 m9 - [3] i; pu - r ? function reserved. o mcoa1 ? motor control pwm channel 1, output a. o usb1_vbus_en ? usb1 vbus power enable. - r ? function reserved. i/o gpio5[18] ? general purpose digital input/output pin. o enet_txd3 ? ethernet transmit data 3 (mii interface). i/o sgpio3 ? general purpose digital input/output pin. o u0_txd ? transmitter output for usart0. p9_6 l11 - [3] i; pu i/o gpio4[11] ? general purpose digital input/output pin. o mcob1 ? motor control pwm channel 1, output b. i usb1_pwr_fault ? usb1 port power fault signal indicating over-current condition; this signal monitors over-current on the usb1 bus (external circuitry required to detect over-current condition). - r ? function reserved. - r ? function reserved. i enet_col ? ethernet collision detect (mii interface). i/o sgpio8 ? general purpose digital input/output pin. i u0_rxd ? receiver input for usart0. pa_0 l12 - [3] i; pu - r ? function reserved. - r ? function reserved. - r ? function reserved. - r ? function reserved. - r ? function reserved. o i2s1_rx_mclk ? i2s1 receive master clock. o cgu_out1 ? cgu spare clock output 1. - r ? function reserved. pa_1 j14 - [4] i; pu i/o gpio4[8] ? general purpose digital input/output pin. i qei_idx ? quadrature encoder in terface index input. - r ? function reserved. o u2_txd ? transmitter output for usart2. - r ? function reserved. - r ? function reserved. - r ? function reserved. - r ? function reserved. table 3. pin description ?continued lcd, ethernet, usb0, and usb1 functions are not available on all parts. see table 2 . symbol lbga256 tfbga100 reset state [2] type description
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 34 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller pa_2 k15 - [4] i; pu i/o gpio4[9] ? general purpose digital input/output pin. i qei_phb ? quadrature encoder interface phb input. - r ? function reserved. i u2_rxd ? receiver input for usart2. - r ? function reserved. - r ? function reserved. - r ? function reserved. - r ? function reserved. pa_3 h11 - [4] i; pu i/o gpio4[10] ? general purpose digital input/output pin. i qei_pha ? quadrature encoder interface pha input. - r ? function reserved. - r ? function reserved. - r ? function reserved. - r ? function reserved. - r ? function reserved. - r ? function reserved. pa_4 g13 - [3] i; pu - r ? function reserved. o ctout_9 ? sct output 9. match output 1 of timer 2. - r ? function reserved. i/o emc_a23 ? external memory address line 23. i/o gpio5[19] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. - r ? function reserved. pb_0 b15 - [3] i; pu - r ? function reserved. o ctout_10 ? sct output 10. match output 2 of timer 2. o lcd_vd23 ? lcd data. - r ? function reserved. i/o gpio5[20] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. - r ? function reserved. table 3. pin description ?continued lcd, ethernet, usb0, and usb1 functions are not available on all parts. see table 2 . symbol lbga256 tfbga100 reset state [2] type description
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 35 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller pb_1 a14 - [3] i; pu - r ? function reserved. i usb1_ulpi_dir ? ulpi link dir signal. controls the ulp data line direction. o lcd_vd22 ? lcd data. - r ? function reserved. i/o gpio5[21] ? general purpose digital input/output pin. o ctout_6 ? sct output 6. match output 2 of timer 1. - r ? function reserved. - r ? function reserved. pb_2 b12 - [3] i; pu - r ? function reserved. i/o usb1_ulpi_d7 ? ulpi link bidirectional data line 7. o lcd_vd21 ? lcd data. - r ? function reserved. i/o gpio5[22] ? general purpose digital input/output pin. o ctout_7 ? sct output 7. match output 3 of timer 1. - r ? function reserved. - r ? function reserved. pb_3 a13 - [3] i; pu - r ? function reserved. i/o usb1_ulpi_d6 ? ulpi link bidirectional data line 6. o lcd_vd20 ? lcd data. - r ? function reserved. i/o gpio5[23] ? general purpose digital input/output pin. o ctout_8 ? sct output 8. match output 0 of timer 2. - r ? function reserved. - r ? function reserved. pb_4 b11 - [3] i; pu - r ? function reserved. i/o usb1_ulpi_d5 ? ulpi link bidirectional data line 5. o lcd_vd15 ? lcd data. - r ? function reserved. i/o gpio5[24] ? general purpose digital input/output pin. i ctin_5 ? sct input 5. capture input 2 of timer 2. - r ? function reserved. - r ? function reserved. table 3. pin description ?continued lcd, ethernet, usb0, and usb1 functions are not available on all parts. see table 2 . symbol lbga256 tfbga100 reset state [2] type description
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 36 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller pb_5 a12 - [3] i; pu - r ? function reserved. i/o usb1_ulpi_d4 ? ulpi link bidirectional data line 4. o lcd_vd14 ? lcd data. - r ? function reserved. i/o gpio5[25] ? general purpose digital input/output pin. i ctin_7 ? sct input 7. o lcd_pwr ? lcd panel power enable. - r ? function reserved. pb_6 a6 - [6] [13] i; pu - r ? function reserved. i/o usb1_ulpi_d3 ? ulpi link bidirectional data line 3. o lcd_vd13 ? lcd data. - r ? function reserved. i/o gpio5[26] ? general purpose digital input/output pin. i ctin_6 ? sct input 6. capture input 1 of timer 3. o lcd_vd19 ? lcd data. - r ? function reserved. ai adc0_6 ? adc0, input channel 6. configure the pin as gpio input and use the adc function select register in the scu to select the adc. pc_0 d4 - [6] [13] i; pu - r ? function reserved. i usb1_ulpi_clk ? ulpi link clk signal. 60 mhz clock generated by the phy. - r ? function reserved. i/o enet_rx_clk ? ethernet receive clock (mii interface). o lcd_dclk ? lcd panel clock. - r ? function reserved. - r ? function reserved. i/o sd_clk ? sd/mmc card clock. ai adc1_1 ? adc1 and adc0, input channel 1. configure the pin as input (usb_ulpi_clk) and use the adc function select register in the scu to select the adc. pc_1 e4 - [3] i; pu i/o usb1_ulpi_d7 ? ulpi link bidirectional data line 7. - r ? function reserved. i u1_ri ? ring indicator input for uart 1. o enet_mdc ? ethernet miim clock. i/o gpio6[0] ? general purpose digital input/output pin. - r ? function reserved. i t3_cap0 ? capture input 0 of timer 3. o sd_volt0 ? sd/mmc bus voltage select output 0. table 3. pin description ?continued lcd, ethernet, usb0, and usb1 functions are not available on all parts. see table 2 . symbol lbga256 tfbga100 reset state [2] type description
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 37 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller pc_2 f6 - [3] i; pu i/o usb1_ulpi_d6 ? ulpi link bidirectional data line 6. - r ? function reserved. i u1_cts ? clear to send input for uart 1. o enet_txd2 ? ethernet transmit data 2 (mii interface). i/o gpio6[1] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. o sd_rst ? sd/mmc reset signal for mmc4.4 card. pc_3 f5 - [6] i; pu i/o usb1_ulpi_d5 ? ulpi link bidirectional data line 5. - r ? function reserved. o u1_rts ? request to send output for uart 1. can also be configured to be an rs-485/eia-485 output enable signal for uart 1. o enet_txd3 ? ethernet transmit data 3 (mii interface). i/o gpio6[2] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. o sd_volt1 ? sd/mmc bus voltage select output 1. ai adc1_0 ? adc1, input channel 0. configure the pin as gpio input and use the adc function select register in the scu to select the adc. pc_4 f4 - [3] i; pu - r ? function reserved. i/o usb1_ulpi_d4 ? ulpi link bidirectional data line 4. - r ? function reserved. enet_tx_en ? ethernet transmit enable (rmii/mii interface). i/o gpio6[3] ? general purpose digital input/output pin. - r ? function reserved. i t3_cap1 ? capture input 1 of timer 3. i/o sd_dat0 ? sd/mmc data bus line 0. pc_5 g4 - [3] i; pu - r ? function reserved. i/o usb1_ulpi_d3 ? ulpi link bidirectional data line 3. - r ? function reserved. o enet_tx_er ? ethernet transmit error (mii interface). i/o gpio6[4] ? general purpose digital input/output pin. - r ? function reserved. i t3_cap2 ? capture input 2 of timer 3. i/o sd_dat1 ? sd/mmc data bus line 1. table 3. pin description ?continued lcd, ethernet, usb0, and usb1 functions are not available on all parts. see table 2 . symbol lbga256 tfbga100 reset state [2] type description
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 38 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller pc_6 h6 - [3] i; pu - r ? function reserved. i/o usb1_ulpi_d2 ? ulpi link bidirectional data line 2. - r ? function reserved. i enet_rxd2 ? ethernet receive data 2 (mii interface). i/o gpio6[5] ? general purpose digital input/output pin. - r ? function reserved. i t3_cap3 ? capture input 3 of timer 3. i/o sd_dat2 ? sd/mmc data bus line 2. pc_7 g5 - [3] i; pu - r ? function reserved. i/o usb1_ulpi_d1 ? ulpi link bidirectional data line 1. - r ? function reserved. i enet_rxd3 ? ethernet receive data 3 (mii interface). i/o gpio6[6] ? general purpose digital input/output pin. - r ? function reserved. o t3_mat0 ? match output 0 of timer 3. i/o sd_dat3 ? sd/mmc data bus line 3. pc_8 n4 - [3] i; pu - r ? function reserved. i/o usb1_ulpi_d0 ? ulpi link bidirectional data line 0. - r ? function reserved. i enet_rx_dv ? ethernet receive data valid (rmii/mii interface). i/o gpio6[7] ? general purpose digital input/output pin. - r ? function reserved. o t3_mat1 ? match output 1 of timer 3. i sd_cd ? sd/mmc card detect input. pc_9 k2 - [3] i; pu - r ? function reserved. i usb1_ulpi_nxt ? ulpi link nxt signal. data flow control signal from the phy. - r ? function reserved. i enet_rx_er ? ethernet receive error (mii interface). i/o gpio6[8] ? general purpose digital input/output pin. - r ? function reserved. o t3_mat2 ? match output 2 of timer 3. o sd_pow ? sd/mmc power monitor output. table 3. pin description ?continued lcd, ethernet, usb0, and usb1 functions are not available on all parts. see table 2 . symbol lbga256 tfbga100 reset state [2] type description
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 39 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller pc_10 m5 - [3] i; pu - r ? function reserved. o usb1_ulpi_stp ? ulpi link stp signal. asserted to end or interrupt transfers to the phy. i u1_dsr ? data set ready input for uart 1. - r ? function reserved. i/o gpio6[9] ? general purpose digital input/output pin. - r ? function reserved. o t3_mat3 ? match output 3 of timer 3. i/o sd_cmd ? sd/mmc command signal. pc_11 l5 - [3] i; pu - r ? function reserved. i usb1_ulpi_dir ? ulpi link dir signal. controls the ulpi data line direction. i u1_dcd ? data carrier detect input for uart 1. - r ? function reserved. i/o gpio6[10] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. i/o sd_dat4 ? sd/mmc data bus line 4. pc_12 l6 - [3] i; pu - r ? function reserved. - r ? function reserved. o u1_dtr ? data terminal ready output for ua rt 1. can also be configured to be an rs-485/eia-485 output enable signal for uart 1. - r ? function reserved. i/o gpio6[11] ? general purpose digital input/output pin. i/o sgpio11 ? general purpose digital input/output pin. i/o i2s0_tx_sda ? i2s transmit data. it is driven by the transmitter and read by the receiver. corresponds to the signal sd in the i 2 s-bus specification . i/o sd_dat5 ? sd/mmc data bus line 5. pc_13 m1 - [3] i; pu - r ? function reserved. - r ? function reserved. o u1_txd ? transmitter output for uart 1. - r ? function reserved. i/o gpio6[12] ? general purpose digital input/output pin. i/o sgpio12 ? general purpose digital input/output pin. i/o i2s0_tx_ws ? transmit word select. it is driven by the master and received by the slave. corresponds to the signal ws in the i 2 s-bus specification . i/o sd_dat6 ? sd/mmc data bus line 6. table 3. pin description ?continued lcd, ethernet, usb0, and usb1 functions are not available on all parts. see table 2 . symbol lbga256 tfbga100 reset state [2] type description
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 40 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller pc_14 n1 - [3] i; pu - r ? function reserved. - r ? function reserved. i u1_rxd ? receiver input for uart 1. - r ? function reserved. i/o gpio6[13] ? general purpose digital input/output pin. i/o sgpio13 ? general purpose digital input/output pin. o enet_tx_er ? ethernet transmit error (mii interface). i/o sd_dat7 ? sd/mmc data bus line 7. pd_0 n2 - [3] i; pu - r ? function reserved. o ctout_15 ? sct output 15. match output 3 of timer 3. o emc_dqmout2 ? data mask 2 used with sdram and static devices. - r ? function reserved. i/o gpio6[14] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. i/o sgpio4 ? general purpose digital input/output pin. pd_1 p1 - [3] i; pu - r ? function reserved. - r ? function reserved. o emc_ckeout2 ? sdram clock enable 2. - r ? function reserved. i/o gpio6[15] ? general purpose digital input/output pin. o sd_pow ? sd/mmc power monitor output. - r ? function reserved. i/o sgpio5 ? general purpose digital input/output pin. pd_2 r1 - [3] i; pu - r ? function reserved. o ctout_7 ? sct output 7. match output 3 of timer 1. i/o emc_d16 ? external memory data line 16. - r ? function reserved. i/o gpio6[16] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. i/o sgpio6 ? general purpose digital input/output pin. table 3. pin description ?continued lcd, ethernet, usb0, and usb1 functions are not available on all parts. see table 2 . symbol lbga256 tfbga100 reset state [2] type description
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 41 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller pd_3 p4 - [3] i; pu - r ? function reserved. o ctout_6 ? sct output 7. match output 2 of timer 1. i/o emc_d17 ? external memory data line 17. - r ? function reserved. i/o gpio6[17] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. i/o sgpio7 ? general purpose digital input/output pin. pd_4 t2 - [3] i; pu - r ? function reserved. o ctout_8 ? sct output 8. match output 0 of timer 2. i/o emc_d18 ? external memory data line 18. - r ? function reserved. i/o gpio6[18] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. i/o sgpio8 ? general purpose digital input/output pin. pd_5 p6 - [3] i; pu - r ? function reserved. o ctout_9 ? sct output 9. match output 1 of timer 2. i/o emc_d19 ? external memory data line 19. - r ? function reserved. i/o gpio6[19] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. i/o sgpio9 ? general purpose digital input/output pin. pd_6 r6 - [3] i; pu - r ? function reserved. o ctout_10 ? sct output 10. match output 2 of timer 2. i/o emc_d20 ? external memory data line 20. - r ? function reserved. i/o gpio6[20] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. i/o sgpio10 ? general purpose digital input/output pin. table 3. pin description ?continued lcd, ethernet, usb0, and usb1 functions are not available on all parts. see table 2 . symbol lbga256 tfbga100 reset state [2] type description
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 42 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller pd_7 t6 - [3] i; pu - r ? function reserved. i ctin_5 ? sct input 5. capture input 2 of timer 2. i/o emc_d21 ? external memory data line 21. - r ? function reserved. i/o gpio6[21] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. i/o sgpio11 ? general purpose digital input/output pin. pd_8 p8 - [3] i; pu - r ? function reserved. i ctin_6 ? sct input 6. capture input 1 of timer 3. i/o emc_d22 ? external memory data line 22. - r ? function reserved. i/o gpio6[22] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. i/o sgpio12 ? general purpose digital input/output pin. pd_9 t11 - [3] i; pu - r ? function reserved. o ctout_13 ? sct output 13. match output 1 of timer 3. i/o emc_d23 ? external memory data line 23. - r ? function reserved. i/o gpio6[23] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. i/o sgpio13 ? general purpose digital input/output pin. pd_10 p11 - [3] i; pu - r ? function reserved. i ctin_1 ? sct input 1. capture input 1 of timer 0. capture input 1 of timer 2. o emc_bls3 ? low active byte lane select signal 3. - r ? function reserved. i/o gpio6[24] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. - r ? function reserved. table 3. pin description ?continued lcd, ethernet, usb0, and usb1 functions are not available on all parts. see table 2 . symbol lbga256 tfbga100 reset state [2] type description
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 43 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller pd_11 n9 - [3] i; pu - r ? function reserved. - r ? function reserved. o emc_cs3 ? low active chip select 3 signal. - r ? function reserved. i/o gpio6[25] ? general purpose digital input/output pin. i/o usb1_ulpi_d0 ? ulpi link bidirectional data line 0. o ctout_14 ? sct output 14. match output 2 of timer 3. - r ? function reserved. pd_12 n11 - [3] i; pu - r ? function reserved. - r ? function reserved. o emc_cs2 ? low active chip select 2 signal. - r ? function reserved. i/o gpio6[26] ? general purpose digital input/output pin. - r ? function reserved. o ctout_10 ? sct output 10. match output 2 of timer 2. - r ? function reserved. pd_13 t14 - [3] i; pu - r ? function reserved. i ctin_0 ? sct input 0. capture input 0 of timer 0, 1, 2, 3. o emc_bls2 ? low active byte lane select signal 2. - r ? function reserved. i/o gpio6[27] ? general purpose digital input/output pin. - r ? function reserved. o ctout_13 ? sct output 13. match output 1 of timer 3. - r ? function reserved. pd_14 r13 - [3] i; pu - r ? function reserved. - r ? function reserved. o emc_dycs2 ? sdram chip select 2. - r ? function reserved. i/o gpio6[28] ? general purpose digital input/output pin. - r ? function reserved. o ctout_11 ? sct output 11. match output 3 of timer 2. - r ? function reserved. table 3. pin description ?continued lcd, ethernet, usb0, and usb1 functions are not available on all parts. see table 2 . symbol lbga256 tfbga100 reset state [2] type description
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 44 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller pd_15 t15 - [3] i; pu - r ? function reserved. - r ? function reserved. i/o emc_a17 ? external memory address line 17. - r ? function reserved. i/o gpio6[29] ? general purpose digital input/output pin. i sd_wp ? sd/mmc card write protect input. o ctout_8 ? sct output 8. match output 0 of timer 2. - r ? function reserved. pd_16 r14 - [3] i; pu - r ? function reserved. - r ? function reserved. i/o emc_a16 ? external memory address line 16. - r ? function reserved. i/o gpio6[30] ? general purpose digital input/output pin. o sd_volt2 ? sd/mmc bus voltage select output 2. o ctout_12 ? sct output 12. match output 0 of timer 3. - r ? function reserved. pe_0 p14 - [3] i; pu - r ? function reserved. - r ? function reserved. - r ? function reserved. i/o emc_a18 ? external memory address line 18. i/o gpio7[0] ? general purpose digital input/output pin. o can1_td ? can1 transmitter output. - r ? function reserved. - r ? function reserved. pe_1 n14 - [3] i; pu - r ? function reserved. - r ? function reserved. - r ? function reserved. i/o emc_a19 ? external memory address line 19. i/o gpio7[1] ? general purpose digital input/output pin. i can1_rd ? can1 receiver input. - r ? function reserved. - r ? function reserved. table 3. pin description ?continued lcd, ethernet, usb0, and usb1 functions are not available on all parts. see table 2 . symbol lbga256 tfbga100 reset state [2] type description
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 45 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller pe_2 m14 - [3] i; pu i adctrig0 ? adc trigger input 0. i can0_rd ? can receiver input. - r ? function reserved. i/o emc_a20 ? external memory address line 20. i/o gpio7[2] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. - r ? function reserved. pe_3 k12 - [3] i; pu - r ? function reserved. o can0_td ? can transmitter output. i adctrig1 ? adc trigger input 1. i/o emc_a21 ? external memory address line 21. i/o gpio7[3] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. - r ? function reserved. pe_4 k13 - [3] i; pu - r ? function reserved. i nmi ? external interrupt input to nmi. - r ? function reserved. i/o emc_a22 ? external memory address line 22. i/o gpio7[4] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. - r ? function reserved. pe_5 n16 - [3] i; pu - r ? function reserved. o ctout_3 ? sct output 3. match output 3 of timer 0. o u1_rts ? request to send output for uart 1. can also be configured to be an rs-485/eia-485 output enable signal for uart 1. i/o emc_d24 ? external memory data line 24. i/o gpio7[5] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. - r ? function reserved. table 3. pin description ?continued lcd, ethernet, usb0, and usb1 functions are not available on all parts. see table 2 . symbol lbga256 tfbga100 reset state [2] type description
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 46 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller pe_6 m16 - [3] i; pu - r ? function reserved. o ctout_2 ? sct output 2. match output 2 of timer 0. i u1_ri ? ring indicator input for uart 1. i/o emc_d25 ? external memory data line 25. i/o gpio7[6] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. - r ? function reserved. pe_7 f15 - [3] i; pu - r ? function reserved. o ctout_5 ? sct output 5. match output 1 of timer 1. i u1_cts ? clear to send input for uart1. i/o emc_d26 ? external memory data line 26. i/o gpio7[7] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. - r ? function reserved. pe_8 f14 - [3] i; pu - r ? function reserved. o ctout_4 ? sct output 4. match output 0 of timer 0. i u1_dsr ? data set ready input for uart 1. i/o emc_d27 ? external memory data line 27. i/o gpio7[8] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. - r ? function reserved. pe_9 e16 - [3] i; pu - r ? function reserved. i ctin_4 ? sct input 4. capture input 2 of timer 1. i u1_dcd ? data carrier detect input for uart 1. i/o emc_d28 ? external memory data line 28. i/o gpio7[9] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. - r ? function reserved. table 3. pin description ?continued lcd, ethernet, usb0, and usb1 functions are not available on all parts. see table 2 . symbol lbga256 tfbga100 reset state [2] type description
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 47 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller pe_10 e14 - [3] i; pu - r ? function reserved. i ctin_3 ? sct input 3. capture input 1 of timer 1. o u1_dtr ? data terminal ready output for ua rt 1. can also be configured to be an rs-485/eia-485 output enable signal for uart 1. i/o emc_d29 ? external memory data line 29. i/o gpio7[10] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. - r ? function reserved. pe_11 d16 - [3] i; pu - r ? function reserved. o ctout_12 ? sct output 12. match output 0 of timer 3. o u1_txd ? transmitter output for uart 1. i/o emc_d30 ? external memory data line 30. i/o gpio7[11] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. - r ? function reserved. pe_12 d15 - [3] i; pu - r ? function reserved. o ctout_11 ? sct output 11. match output 3 of timer 2. i u1_rxd ? receiver input for uart 1. i/o emc_d31 ? external memory data line 31. i/o gpio7[12] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. - r ? function reserved. pe_13 g14 - [3] i; pu - r ? function reserved. o ctout_14 ? sct output 14. match output 2 of timer 3. i/o i2c1_sda ? i 2 c1 data input/output (this pin does not use a specialized i 2 c pad). o emc_dqmout3 ? data mask 3 used with sdram and static devices. i/o gpio7[13] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. - r ? function reserved. table 3. pin description ?continued lcd, ethernet, usb0, and usb1 functions are not available on all parts. see table 2 . symbol lbga256 tfbga100 reset state [2] type description
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 48 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller pe_14 c15 - [3] i; pu - r ? function reserved. - r ? function reserved. - r ? function reserved. o emc_dycs3 ? sdram chip select 3. i/o gpio7[14] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. - r ? function reserved. pe_15 e13 - [3] i; pu - r ? function reserved. o ctout_0 ? sct output 0. match output 0 of timer 0. i/o i2c1_scl ? i 2 c1 clock input/output (this pin does not use a specialized i 2 c pad). o emc_ckeout3 ? sdram clock enable 3. i/o gpio7[15] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. - r ? function reserved. pf_0 d12 - [3] o; pu i/o ssp0_sck ? serial clock for ssp0. i gp_clkin ? general purpose clock input to the cgu. - r ? function reserved. - r ? function reserved. - r ? function reserved. - r ? function reserved. - r ? function reserved. o i2s1_tx_mclk ? i2s1 transmit master clock. pf_1 e11 - [3] i; pu - r ? function reserved. - r ? function reserved. i/o ssp0_ssel ? slave select for ssp0. - r ? function reserved. i/o gpio7[16] ? general purpose digital input/output pin. - r ? function reserved. i/o sgpio0 ? general purpose digital input/output pin. - r ? function reserved. table 3. pin description ?continued lcd, ethernet, usb0, and usb1 functions are not available on all parts. see table 2 . symbol lbga256 tfbga100 reset state [2] type description
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 49 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller pf_2 d11 - [3] i; pu - r ? function reserved. o u3_txd ? transmitter output for usart3. i/o ssp0_miso ? master in slave out for ssp0. - r ? function reserved. i/o gpio7[17] ? general purpose digital input/output pin. - r ? function reserved. i/o sgpio1 ? general purpose digital input/output pin. - r ? function reserved. pf_3 e10 - [3] i; pu - r ? function reserved. i u3_rxd ? receiver input for usart3. i/o ssp0_mosi ? master out slave in for ssp0. - r ? function reserved. i/o gpio7[18] ? general purpose digital input/output pin. - r ? function reserved. i/o sgpio2 ? general purpose digital input/output pin. - r ? function reserved. pf_4 d10 h4 [3] o; pu i/o ssp1_sck ? serial clock for ssp1. i gp_clkin ? general purpose clock input to the cgu. o traceclk ? trace clock. - r ? function reserved. - r ? function reserved. - r ? function reserved. o i2s0_tx_mclk ? i2s transmit master clock. i/o i2s0_rx_sck ? i2s receive clock. it is driven by the master and received by the slave. corresponds to the signal sck in the i 2 s-bus specification . pf_5 e9 - [6] i; pu - r ? function reserved. i/o u3_uclk ? serial clock input/output for usart3 in synchronous mode. i/o ssp1_ssel ? slave select for ssp1. o tracedata[0] ? trace data, bit 0. i/o gpio7[19] ? general purpose digital input/output pin. - r ? function reserved. i/o sgpio4 ? general purpose digital input/output pin. - r ? function reserved. ai adc1_4 ? adc1, input channel 4. configure the pin as gpio input and use the adc function select register in the scu to select the adc. table 3. pin description ?continued lcd, ethernet, usb0, and usb1 functions are not available on all parts. see table 2 . symbol lbga256 tfbga100 reset state [2] type description
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 50 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller pf_6 e7 - [6] i; pu - r ? function reserved. i/o u3_dir ? rs-485/eia-485 output enable/direction control for usart3. i/o ssp1_miso ? master in slave out for ssp1. o tracedata[1] ? trace data, bit 1. i/o gpio7[20] ? general purpose digital input/output pin. - r ? function reserved. i/o sgpio5 ? general purpose digital input/output pin. i/o i2s1_tx_sda ? i2s1 transmit data. it is driven by the transmitter and read by the receiver. corresponds to the signal sd in the i 2 s-bus specification . ai adc1_3 ? adc1, input channel 3. configure the pin as gpio input and use the adc function select register in the scu to select the adc. pf_7 b7 - [6] i; pu - r ? function reserved. i/o u3_baud ? baud pin for usart3. i/o ssp1_mosi ? master out slave in for ssp1. o tracedata[2] ? trace data, bit 2. i/o gpio7[21] ? general purpose digital input/output pin. - r ? function reserved. i/o sgpio6 ? general purpose digital input/output pin. i/o i2s1_tx_ws ? transmit word select. it is driven by the master and received by the slave. corresponds to the signal ws in the i 2 s-bus specification . ai/ o adc1_7 ? adc1, input channel 7 or band gap output. configure the pin as gpio input and use the adc function select register in the scu to select the adc. pf_8 e6 - [6] [13] i; pu - r ? function reserved. i/o u0_uclk ? serial clock input/output for usart0 in synchronous mode. i ctin_2 ? sct input 2. capture input 2 of timer 0. o tracedata[3] ? trace data, bit 3. i/o gpio7[22] ? general purpose digital input/output pin. - r ? function reserved. i/o sgpio7 ? general purpose digital input/output pin. - r ? function reserved. ai adc0_2 ? adc0, input channel 2. configure the pin as gpio input and use the adc function select register in the scu to select the adc. table 3. pin description ?continued lcd, ethernet, usb0, and usb1 functions are not available on all parts. see table 2 . symbol lbga256 tfbga100 reset state [2] type description
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 51 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller pf_9 d6 - [6] [13] i; pu - r ? function reserved. i/o u0_dir ? rs-485/eia-485 output enable/direction control for usart0. o ctout_1 ? sct output 1. match output 1 of timer 0. - r ? function reserved. i/o gpio7[23] ? general purpose digital input/output pin. - r ? function reserved. i/o sgpio3 ? general purpose digital input/output pin. - r ? function reserved. ai adc1_2 ? adc1, input channel 2. configure the pin as gpio input and use the adc function select register in the scu to select the adc. pf_10 a3 - [6] [13] i; pu - r ? function reserved. o u0_txd ? transmitter output for usart0. - r ? function reserved. - r ? function reserved. i/o gpio7[24] ? general purpose digital input/output pin. - r ? function reserved. i sd_wp ? sd/mmc card write protect input. - r ? function reserved. ai adc0_5 ? adc0, input channel 5. configure the pin as gpio input and use the adc function select register in the scu to select the adc. pf_11 a2 - [6] [13] i; pu - r ? function reserved. i u0_rxd ? receiver input for usart0. - r ? function reserved. - r ? function reserved. i/o gpio7[25] ? general purpose digital input/output pin. - r ? function reserved. o sd_volt2 ? sd/mmc bus voltage select output 2. - r ? function reserved. ai adc1_5 ? adc1, input channel 5. configure the pin as gpio input and use the adc function select register in the scu to select the adc. table 3. pin description ?continued lcd, ethernet, usb0, and usb1 functions are not available on all parts. see table 2 . symbol lbga256 tfbga100 reset state [2] type description
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 52 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller clock pins clk0 n5 k3 [5] o; pu o emc_clk0 ? sdram clock 0. o clkout ? clock output pin. - r ? function reserved. - r ? function reserved. i/o sd_clk ? sd/mmc card clock. o emc_clk01 ? sdram clock 0 and clock 1 combined. i/o ssp1_sck ? serial clock for ssp1. i enet_tx_clk (enet_ref_clk) ? ethernet transmit clock (mii interface) or ethernet refe rence clock (rmii interface). clk1 t10 - [5] o; pu o emc_clk1 ? sdram clock 1. o clkout ? clock output pin. - r ? function reserved. - r ? function reserved. - r ? function reserved. o cgu_out0 ? cgu spare clock output 0. - r ? function reserved. o i2s1_tx_mclk ? i2s1 transmit master clock. clk2 d14 k6 [5] o; pu o emc_clk3 ? sdram clock 3. o clkout ? clock output pin. - r ? function reserved. - r ? function reserved. i/o sd_clk ? sd/mmc card clock. o emc_clk23 ? sdram clock 2 and clock 3 combined. o i2s0_tx_mclk ? i2s transmit master clock. i/o i2s1_rx_sck ? receive clock. it is driven by the master and received by the slave. corresponds to the signal sck in the i 2 s-bus specification. clk3 p12 - [5] o; pu o emc_clk2 ? sdram clock 2. o clkout ? clock output pin. - r ? function reserved. - r ? function reserved. - r ? function reserved. o cgu_out1 ? cgu spare clock output 1. - r ? function reserved. i/o i2s1_rx_sck ? receive clock. it is driven by the master and received by the slave. corresponds to the signal sck in the i 2 s-bus specification. debug pins dbgen l4 a6 [3] i i jtag interface control signal. also used for boundary scan. table 3. pin description ?continued lcd, ethernet, usb0, and usb1 functions are not available on all parts. see table 2 . symbol lbga256 tfbga100 reset state [2] type description
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 53 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller tck/swdclk j5 h2 [3] i; f i test clock for jtag interface (d efault) or serial wire (sw) clock. trst m4 b4 [3] i; pu i test reset for jtag interface. tms/swdio k6 c4 [3] i; pu i test mode select for jtag interface (default) or sw debug data input/output. tdo/swo k5 h3 [3] o o test data out for jtag interface (default) or sw trace output. tdi j4 g3 [3] i; pu i test data in for jtag interface. usb0 pins usb0_dp f2 e1 [7] - i/o usb0 bidirectional d+ line. usb0_dm g2 e2 [7] - i/o usb0 bidirectional d ? line. usb0_vbus f1 e3 [7] [8] - i/o vbus pin (power on usb cable). this pin includes an internal pull-down resistor of 64 k ? (typical) ? 16 k ? . usb0_id h2 f1 [9] - i indicates to the transceiver whether connected as an a-device (usb0_id low) or b-device (usb0_id high). for otg this pin has an internal pull-up resistor. usb0_rref h1 f3 [9] - 12.0 k ? (accuracy 1 %) on-board resistor to ground for current reference. usb1 pins usb1_dp f12 e9 [10] - i/o usb1 bidirectional d+ line. usb1_dm g12 e10 [10] - i/o usb1 bidirectional d ? line. i 2 c-bus pins i2c0_scl l15 d6 [11] i; f i/o i 2 c clock input/output. op en-drain output (for i 2 c-bus compliance). i2c0_sda l16 e6 [11] i; f i/o i 2 c data input/output. open-drain output (for i 2 c-bus compliance). reset and wake-up pins reset d9 b6 [12] i; ia i external reset input: a low-going pulse as short as 50 ns on this pin resets the device, causing i/o ports and periphera ls to take on their default states, and processor execution to begin at address 0. wakeup0 a9 a4 [12] i; ia i external wake-up input; can raise an interrupt and can cause wake-up from any of the low power modes. wakeup1 a10 - [12] i; ia i external wake-up input; can raise an interrupt and can cause wake-up from any of the low power modes. wakeup2 c9 - [12] i; ia i external wake-up input; can raise an interrupt and can cause wake-up from any of the low power modes. wakeup3 d8 - [12] i; ia i external wake-up input; can raise an interrupt and can cause wake-up from any of the low power modes. table 3. pin description ?continued lcd, ethernet, usb0, and usb1 functions are not available on all parts. see table 2 . symbol lbga256 tfbga100 reset state [2] type description
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 54 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller adc pins adchs_0 e3 a2 [9] i; ia i 12-bit high-speed adc input channel 0. adchs_1 c3 a1 [9] i; ia i 12-bit high-speed adc input channel 1. adchs_2 a4 b3 [9] i; ia i 12-bit high-speed adc input channel 2. adchs_3 a5 - [9] i; ia i 12-bit high-speed adc input channel 3. adchs_4 c6 - [9] i; ia i 12-bit high-speed adc input channel 4. adchs_5 b3 - [9] i; ia i 12-bit high-speed adc input channel 5. adchs_neg b5 a3 [9] i; ia i/o 12-bit high-speed adc reference vo ltage output or negative differential input. adc0_7 c5 - [9] i; ia i 10-bit adc0 input channel 7. rtc rtc_alarm a11 c3 [12] - o rtc controlled output. rtcx1 a8 a5 [9] - i input to the rtc 32 khz ultra-low power oscillator circuit. rtcx2 b8 b5 [9] - o output from the rtc 32 khz ultra-low power oscillator circuit. crystal oscillator pins xtal1 d1 b1 [9] - i input to the oscillator circuit and internal clock generator circuits. xtal2 e1 c1 [9] - o output from the oscillator amplifier. power and ground pins usb0_vdda 3v3_driver f3 d1 - - separate analog 3.3 v power supply for driver. usb0 _vdda3v3 g3 d2 - - usb 3.3 v separate power supply voltage. usb0_vssa _term h3 d3 - - dedicated analog ground for clean reference for termination resistors. usb0_vssa _ref g1 f2 - - dedicated clean analog ground for generation of reference currents and voltages. vdda b4 b2 - - analog power supply and 10-bit adc reference voltage. vbat b10 c5 - - rtc power supply: 3.3 v on this pin supplies power to the rtc. vddreg f10, f9, l8, l7 e4, e5, f4 - main regulator power supply. tie the vddreg and vddio pins to a common power supply to ensure the same ramp-up time for both supply voltages. vpp e8 - - - otp programming voltage. table 3. pin description ?continued lcd, ethernet, usb0, and usb1 functions are not available on all parts. see table 2 . symbol lbga256 tfbga100 reset state [2] type description
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 55 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller [1] - = not pinned out. [2] i = input, o = output, ai/o analog input/output, ia = inactive; pu = pull-up enabled (weak pul l-up resistor pulls up pin to v dd(io) ); f = floating. reset state reflects the pin state at reset without boot code operation. [3] 5 v tolerant pad with 15 ns glitch filter (5 v tolerant if v dd(io) present; if v dd(io) not present, do not exceed 3.3 v); provides digital i/o functions with ttl levels and hy steresis; normal drive strength. [4] 5 v tolerant pad with 15 ns glitch filter (5 v tolerant if v dd(io) present; if v dd(io) not present, do not exceed 3.3 v) providing digital i/o functions with ttl levels, and hysteresis; high drive strength. [5] 5 v tolerant pad with 15 ns glitch filter (5 v tolerant if v dd(io) present; if v dd(io) not present, do not exceed 3.3 v) providing high-speed digital i/o functions with ttl levels and hysteresis. vddio d7, e12, f7, f8, g10, h10, j6, j7, k7, l9, l10, n7, n13 f10, k5 - - i/o power supply. tie the vddreg and vddio pins to a common power supply to ensure the same ramp-up time for both supply voltages. vdd - - power supply for main regulator, i/o, and otp. vss g9, h7, j10, j11, k8 - - - ground. vssio c4, d13, g6, g7, g8, h8, h9, j8, j9, k9, k10, m13, p7, p13 c8, d4, d5, g8, j3, j6 - - ground. vssa b2 c2 - - analog ground. not connected -b9---n.c. table 3. pin description ?continued lcd, ethernet, usb0, and usb1 functions are not available on all parts. see table 2 . symbol lbga256 tfbga100 reset state [2] type description
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 56 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller [6] 5 v tolerant pad providing digital i/o functions (with ttl levels and hysteresis) and analog input or output (5 v tolerant i f v dd(io) present; if v dd(io) not present, do not exceed 3.3 v). when configured as a adc input or dac output, the pin is not 5 v tolerant and the digital section of the pad must be disabled by setting the pin to an input function and disabling the pull-up resistor through the pin? s sfsp register. [7] 5 v tolerant transparent analog pad. [8] for maximum load c l = 6.5 ? f and maximum resistance r pd = 80 k ? , the vbus signal takes about 2 s to fall from vbus = 5 v to vbus = 0.2 v when it is no longer driven. [9] transparent analog pad. not 5 v tolerant. [10] pad provides usb functions (5 v tolerant if v dd(io) present; if v dd(io) not present, do not exceed 3.3 v). it is designed in accordance with the usb specification, revision 2.0 (full-speed and low-speed mode only). [11] open-drain 5 v tolerant digital i/o pad, compatible with i 2 c-bus fast mode plus specification. this pad requires an external pull-up to provide output functionality. when power is switched off, this pin connected to the i 2 c-bus is floating and does not disturb the i 2 c lines. [12] 5 v tolerant pad with 20 ns glitch filter; provides digita l i/o functions with open-drain output with weak pull-up resistor and hysteresis. [13] to minimize interference on the 12-bi t adc signal lines, do not configure the di gital signal as output when using the 12-bi t adc. see table 42 .
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 57 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller 7. functional description 7.1 architectural overview the arm cortex-m4 includes th ree ahb-lite buses: the system bus, the i-code bus, and the d-code bus. the i-code and d-code core buses allow for concurrent code and data accesses from different slave ports. the lpc4370 use a multi-layer ahb matrix to connect the arm cortex-m4 buses and other bus masters to peripherals in a flexible manner that optimizes performance by allowing peripherals that are on different slav es ports of the matrix to be accessed simultaneously by different bus masters. an arm cortex-m0 coprocessor is included in the lpc4370, capable of off-loading the main arm cortex-m4 application processor. mo st peripheral interrupts are connected to both processors. the processors communicate with each other via an interprocessor communication protocol. 7.2 arm cortex-m4 processor the arm cortex-m4 cpu incorporates a 3-stage pipeline, uses a ha rvard architecture with separate local instruction and data buses as well as a third bus for peripherals, and includes an internal prefetch unit that supports speculative branching. the arm cortex-m4 supports single-cycle digital si gnal processing and simd instructions. a hardware floating-point processor is integrat ed in the core. the processor includes a nvic with up to 53 interrupts. 7.3 arm cortex-m0 processors the arm cortex-m0 processors are general purpose, 32-bit microprocessors, which offer high performance and very low power consum ption. the arm cortex-m0 processor uses a 3-stage pipeline von neumann architecture and a small but powerful instruction set providing high-end processing hardware. th e processors each incorporate an nvic with 32 interrupts. 7.3.1 arm cortex-m0 coprocessor the m0 coprocessor resides on the same ahb multi-layer matrix as the main cortex-m0 core. the coprocessor can be used to off-load multiple tasks from the main cortex-m4 processor. 7.3.2 arm cortex-m0 subsytem the cortex-m0 subsystem can be used to ma nage the sgpio and spi peripherals on the m0 subsystem multilayer matrix but any other peripheral as well. the m0 subsystem is separated by a bridge from the main ahb ma trix. the m0 subsystem ahb matrix has two sram blocks which allows to run the cort ex-m0 subsytem at full speed independently from the main matrix. one application of using the subsystem is to reduce power, for example when the main matrix runs at a very low speed and the m0 subsystem monitors activity and increases the main matrix speed when needed.
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 58 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller one of the two sram blocks connected to the subsystem ahb matrix is typically used for code running on the m0 subsystem and the other sram block for data. this allows other bus masters to access the data sram without interrupting the m0 processor instruction fetches and thereby stalling the m0 subsystem. the m0 subsystem matrix runs at an asynchronous speed from the main matrix. this allows to operate the sgpio at any desired frequency. the m0 subsystem can control the sgpio in a deterministic way, without incurring latency that occurs when the m4 controls the sgpio through a bridge. 7.4 interprocessor communication the arm cortex-m4 and arm cortex-m0 inte rprocessor communication is based on using shared sram as mailbox and one processor raising an interrupt on the other processor's nvic, for example after it has delivered a new message in the mailbox. the receiving processor can reply by raising an interrupt on the sending processor's nvic to acknowledge the message.
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 59 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller 7.5 ahb multilayer matrix 7.6 nested vectored inte rrupt controller (nvic) the nvic is an integral part of the cortex-m 4. the tight coupling to the cpu allows for low interrupt latency and efficient processing of late arriving interrupts. fig 4. ahb multilayer matrix master and slave connections arm cortex-m4 test/debug interface arm cortex-m0 test/debug interface dma ethernet usb1 usb0 lcd sd/ mmc external memory controller apb, rtc domain peripherals 16 kb + 16 kb ahb sram 64 kb rom 128 kb local sram 72 kb local sram system bus i- code bus d- code bus masters slaves 01 ahb multilayer matrix = master-slave connection 32 kb ahb sram spifi sgpio ahb peripherals register interfaces 002aaf873 high-speed phy
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 60 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller each arm cortex-m0 coprocessor has its own nvic with 32 vectored interrupts. most peripheral interrupts are shared between the two cortex-m0cores and the cortex-m4 nvics. 7.6.1 features ? arm cortex-m4 nvic: ? controls system exceptions and peripheral interrupts. ? up to 53 vectored interrupts. ? eight programmable interrupt priority leve ls with hardware prio rity level masking. ? relocatable vector table. ? non-maskable interrupt (nmi). ? software interrupt generation. ? arm cortex-m0 and arm co rtex-m0 subsystem nvic: ? control system exceptions and peripheral interrupts. ? up to 32 vectored interrupts. ? four programmable priority levels with hardware priority level masking. 7.6.2 interrupt sources each peripheral device has one interrupt line connected to the nvic but may have several interrupt flags. individual interrupt flags may also represent more than one interrupt source. 7.7 system tick timer (systick) the arm cortex-m4 includes a system tick timer (systic k) that is inte nded to generate a dedicated systick exception at a 10 ms interval. 7.8 event router the event router combines various internal signals, interrupts, and the external interrupt pins (wakeup[3:0]) to create an interrupt in the nvic if enabled and to create a wake-up signal to the arm core and the ccu for wa king up from sleep, deep-sleep, power-down, and deep power-down modes. individual events can be configured as edge or level sensitive and can be enabled or disabled in the event router. the event router can be battery powered. the following events if enabled in the event router can create a wake-up signal and/or an interrupt: ? external pins wakeu p0/1/2/3 and reset ? alarm timer, rtc, wwdt, bod interrupts ? c_can and qei interrupts ? ethernet, usb0, usb1 signals ? selected outputs of combined timers (sct and timer0/1/3)
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 61 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller 7.9 global input mult iplexer array (gima) the gima allows to route signals to event-d riven peripheral targets like the sct, timers, event router, or the adcs. 7.9.1 features ? single selectio n of a source. ? signal inversion. ? can capture a pulse if the input event source is faster than the target clock. ? synchronization of input event and target clock. ? single-cycle pulse generation for target. 7.10 system tick timer (systick) the arm cortex-m4 includes a system tick timer (systic k) that is inte nded to generate a dedicated systick exception at a 10 ms interval. 7.11 on-chip static ram the lpc4370 support 200 kb local sram and an additional 64 kb ahb sram with separate bus master access for higher throughput and individual power control for low power operation. see section 7.23.9.1 ? memory retention in power-down modes ? . 7.12 in-system programming (isp) in-system programming (isp) is programmi ng or reprogramming the on-chip sram memory, using the boot loader software and the usart0 serial port. this can be done when the part resides in the end-user board. isp allows to load data into on-chip sram and execute code from on-chip sram. 7.13 boot rom the internal rom memory is used to store th e boot code of the lpc4370. after a reset, the arm processor will start its code execution from this memory. the boot rom memory includes the following features: ? rom memory size is 64 kb. ? supports booting from uart interfaces and external static memory such as nor flash, spi flash, quad spi flash. ? includes apis for otp programming. ? includes a flexible usb device stack that supports human interface device (hid), mass storage class (msc), and device firmware upgrade (dfu) drivers. several boot modes are available depending on the values of the otp bits boot_src. if the otp memory is not programmed or the boot_src bits are all zero, the boot mode is determined by the states of the bo ot pins p2_9, p2_8, p1_2, and p1_1.
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 62 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller [1] the boot loader programs the appropriate pin functi on at reset to boot using either ssp0 or spifi. remark: pin functions for spifi and ssp0 boot are different. [1] the boot loader programs the appropriate pin functi on at reset to boot using either ssp0 or spifi. table 4. boot mode when otp boot_src bits are programmed boot mode boot_src bit 3 boot_src bit 2 boot_src bit 1 boot_src bit 0 description pin state 0 0 0 0 boot source is defined by the reset state of p1_1, p1_2, p2_8 pins, and p2_9. see ta b l e 5 . usart0 0 0 0 1 boot from device connected to usart0 using pins p2_0 and p2_1. spifi 0 0 1 0 boot from quad spi flash connected to the spifi interface using pins p3_3 to p3_8. emc 8-bit 0 0 1 1 boot from external static memory (such as nor flash) using cs0 and an 8-bit data bus. emc 16-bit 0 1 0 0 boot from external static memory (such as nor flash) using cs0 and a 16-bit data bus. emc 32-bit 0 1 0 1 boot from external static memory (such as nor flash) using cs0 and a 32-bit data bus. u s b 0011 0b o o t f r o m u s b 0 . u s b 1011 1b o o t f r o m u s b 1 . spi (ssp) 1 0 0 0 boot from spi flash connected to the ssp0 interface on p3_3 (function ssp0_sck), p3_6 (function ssp0_ssel) , p3_7 (function ssp0_miso), and p3_8 (function ssp0_mosi) [1] . usart3 1 0 0 1 boot from device connected to usart3 using pins p2_3 and p2_4. table 5. boot mode when opt boot_src bits are zero boot mode pins description p2_9 p2_8 p1_2 p1_1 usart0 low low low low boot from device connected to usart0 using pins p2_0 and p2_1. spifi low low low high boot from quad spi flash connected to the spifi interface on p3_3 to p3_8 [1] . emc 8-bit low low high low boot from external static memory (such as nor flash) using cs0 and an 8-bit data bus. emc 16-bit low low high high boot from ex ternal static memory (such as nor flash) using cs0 and a 16-bit data bus. emc 32-bit low high low low boot from external static memory (such as nor flash) using cs0 and a 32-bit data bus. usb0 low high low high boot from usb0 usb1 low high high low boot from usb1. spi (ssp) low high high high boot from spi flash connected to the ssp0 interface on p3_3 (function ssp0_sck), p3_6 (function ssp0_ssel), p3_7 (function ssp0_miso), and p3_8 (function ssp0_mosi) [1] . usart3 high low low low boot from device connected to usart3 using pins p2_3 and p2_4.
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 63 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller remark: pin functions for spifi and ssp0 boot are different. 7.14 memory mapping the memory map shown in figure 5 and figure 6 is global to both the cortex-m4 and the cortex-m0 processors and all sram is shared between both processors. each processor uses its own arm private bus memory map for the nvic and other system functions.
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 64 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller fig 5. lpc4370 memory mapping (overview) reserved peripheral bit band alias region reserved reserved high-speed gpio 12-bit adc (adchs) 0x0000 0000 0 gb 1 gb 4 gb 0x2001 0000 0x2200 0000 0x2400 0000 0x2800 0000 0x1000 0000 0x3000 0000 0x4000 0000 0x4001 2000 0x4004 0000 0x4005 0000 0x4010 0000 0x4400 0000 0x6000 0000 ahb peripherals apb peripherals #0 apb peripherals #1 reserved reserved reserved rtc domain peripherals 0x4006 0000 0x4008 0000 0x4009 0000 0x400a 0000 0x400b 0000 0x400c 0000 0x400d 0000 0x400e 0000 0x400f 0000 0x400f 1000 0x400f 2000 0x400f 4000 0x400f 8000 clocking/reset peripherals apb peripherals #2 apb peripherals #3 0x2000 8000 16 kb ahb sram 16 kb ahb sram 0x2000 c000 16 kb ahb sram 16 kb ahb sram sgpio spi 0x4010 1000 0x4010 2000 0x4200 0000 reserved local sram/ external static memory banks 0x2000 0000 0x2000 4000 128 mb dynamic external memory dycs0 256 mb dynamic external memory dycs1 256 mb dynamic external memory dycs2 256 mb dynamic external memory dycs3 0x7000 0000 0x8000 0000 0x8800 0000 0xe000 0000 256 mb shadow area lpc4370 0x1000 0000 0x1002 0000 0x1008 0000 0x1008 a000 0x1009 2000 0x1040 0000 0x1041 0000 0x1c00 0000 0x1d00 0000 reserved reserved 32 mb ahb sram bit banding reserved reserved reserved 0xe010 0000 0xffff ffff reserved spifi data arm private bus reserved 0x1001 8000 32 kb local sram 96 kb local sram 32 kb + 8 kb local sram 32 kb local sram reserved reserved reserved reserved 64 kb rom 0x1400 0000 0x1800 0000 0x1800 4000 spifi data 0x1e00 0000 0x1f00 0000 0x2000 0000 16 mb static external memory cs3 16 mb static external memory cs2 16 mb static external memory cs1 16 mb static external memory cs0 002aag610 16 kb m0 subsystem sram 0x1800 4800 2 kb m0 subsystem sram
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 65 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller fig 6. lpc4370 memory mapping (peripherals) reserved peripheral bit band alias region high-speed gpio 12-bit adc (adchs) reserved reserved 0x4000 0000 0x0000 0000 0x4001 2000 0x4004 0000 0x4005 0000 0x4010 0000 0x4400 0000 0x6000 0000 0xffff ffff ahb peripherals sram memories external memory banks apb0 peripherals apb1 peripherals reserved reserved reserved rtc domain peripherals 0x4006 0000 0x4008 0000 0x4009 0000 0x400a 0000 0x400b 0000 0x400c 0000 0x400d 0000 0x400e 0000 0x400f 0000 0x400f 1000 0x400f 2000 0x400f 4000 0x400f 8000 clocking/reset peripherals apb2 peripherals apb3 peripherals sgpio spi reserved 0x4010 1000 0x4010 2000 0x4200 0000 reserved external memories and arm private bus apb2 peripherals 0x400c 1000 0x400c 2000 0x400c 3000 0x400c 4000 0x400c 6000 0x400c 8000 0x400c 7000 0x400c 5000 0x400c 0000 ri timer usart2 usart3 timer2 timer3 ssp1 qei apb1 peripherals 0x400a 1000 0x400a 2000 0x400a 3000 0x400a 4000 0x400a 5000 0x400b 0000 0x400a 0000 motor control pwm i2c0 i2s0 i2s1 c_can1 reserved ahb peripherals 0x4000 1000 0x4000 0000 sct 0x4000 2000 0x4000 3000 0x4000 4000 0x4000 6000 0x4000 8000 0x4001 0000 0x4001 2000 0x4000 9000 0x4000 7000 0x4000 5000 dma sd/mmc emc usb1 lcd usb0 reserved spifi ethernet reserved 0x4008 1000 0x4008 0000 wwdt 0x4008 2000 0x4008 3000 0x4008 4000 0x4008 6000 0x4008 a000 0x4008 7000 0x4008 8000 0x4008 9000 0x4008 5000 uart1 w/ modem ssp0 timer0 timer1 scu gpio interrupts gpio group0 interrupt gpio group1 interrupt usart0 rtc domain peripherals 0x4004 1000 0x4004 0000 alarm timer 0x4004 2000 0x4004 3000 0x4004 4000 0x4004 6000 0x4004 7000 0x4004 5000 power mode control creg event router otp controller reserved reserved rtc backup registers clocking reset control peripherals 0x4005 1000 0x4005 0000 cgu 0x4005 2000 0x4005 3000 0x4005 4000 0x4006 0000 ccu2 rgu ccu1 lpc4370 002aag611 reserved reserved apb3 peripherals 0x400e 1000 0x400e 2000 0x400e 3000 0x400e 4000 0x400f 0000 0x400e 5000 0x400e 0000 i2c1 dac c_can0 10-bit adc0 10-bit adc1 reserved gima apb0 peripherals
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 66 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller 7.15 one-time program mable (otp) memory the otp provides 64-bit + 256 bit of memory for general purpose use. 7.16 general purpose i/o (gpio) the lpc4370 provide 8 gpio ports with up to 31 gpio pins each. device pins that are not connec ted to a specific peripheral function are controlled by the gpio registers. pins may be dynamically conf igured as inputs or outputs. separate registers allow setting or clearing any number of outputs simultaneously. the value of the output register may be read back as well as the current state of the port pins. all gpio pins default to inputs with pull-up resistors enabled on reset. 7.16.1 features ? accelerated gpio functions: ? gpio registers are located on the ahb so that the fastest possible i/o timing can be achieved. ? mask registers allow treating sets of port bits as a group, leaving other bits unchanged. ? all gpio registers are byte and half-word addressable. ? entire port value can be written in one instruction. ? bit-level set and clear registers allow a single instruction set or clear of any number of bits in one port. ? direction control of individual bits. ? all i/o default to inputs after reset. ? up to eight gpio pins can be selected from all gpio pins to create an edge- or level-sensitive gpio interrupt request (gpio interrupts). ? two gpio group interrupts can be triggered by any pin or pins in each port (gpio group0 and group1 interrupts). 7.17 configurable di gital peripherals 7.17.1 state configurable timer (sct) subsystem the sct allows a wide variety of timing, counting, output modulation, and input capture operations. the inputs and outputs of the sct are shared with t he capture and match inputs/outputs of the 32-bit general purpose counter/timers. the sct can be configured as two 16-bit counters or a unified 32-bit counter. in the two-counter case, in addition to the counter value the following operational elements are independent for each half: ? state variable ? limit, halt, stop, and start conditions ? values of match/capture registers, plus reload or capture control values
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 67 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller in the two-counter case, the following operational elements are global to the sct, but the last three can use match cond itions from either counter: ? clock selection ? inputs ? events ? outputs ? interrupts 7.17.1.1 features ? two 16-bit counters or one 32-bit counter. ? counter(s) clocked by bu s clock or selected input. ? up counter(s) or up-down counter(s). ? state variable allows sequencin g across multiple counter cycles. ? event combines input or output condition and/or counter match in a specified state. ? events control outputs and interrupts. ? selected event(s) can limit, halt, start, or stop a counter. ? supports: ? 8 inputs (one input connected internally) ? 16 outputs ? 16 match/capture registers ? 16 events ? 32 states 7.17.2 serial gpio (sgpio) the serial gpios offer standard gpio functi onality enhanced with features to accelerate serial stream processing. 7.17.2.1 features ? each sgpio input/output slice can be used to perform a serial to parallel or parallel to serial data conversion. ? 16 sgpio input/output slices each with a 32-bit fifo that can shift the input value from a pin or an output value to a pin with every cycle of a shift clock. ? each slice is double-buffered. ? interrupt is generated on a full fi fo, shift clock, or pattern match. ? slices can be concatenated to increase buffer size. ? each slice has a 32-bit pattern match filter.
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 68 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller 7.18 ahb peripherals 7.18.1 general purpose dma (gpdma) the dma controller allows peripheral-to memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. each dma stream provides unidirectional serial dma transfer s for a single source and destination. for example, a bidirectional port requires one st ream for transmit and one for receives. the source and destination areas can each be either a memory region or a peripheral for master 1, but only memory for master 0. 7.18.1.1 features ? eight dma channels. each channel can support an unidirectional transfer. ? 16 dma request lines. ? single dma and burst dma request signals. each peripheral connected to the dma controller can assert either a burst dma request or a single dma request. the dma burst size is set by programming the dma controller. ? memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral transfers are supported. ? scatter or gather dma is supported through the use of linked lists. this means that the source and destination areas do not hav e to occupy contiguous areas of memory. ? hardware dma ch annel priority. ? ahb slave dma programming interface. the dma controller is programmed by writing to the dma control regist ers over the ahb slave interface. ? two ahb bus masters for transferring data. these interfaces transfer data when a dma request goes active. master 1 can access memories and peripherals (except sgpio and spi). master 0 can access memories on the main ahb matrix and peripherals and memories on the m0sub bus. ? 32-bit ahb master bus width. ? incrementing or non-incrementing addressing for source and destination. ? programmable dma burst size. the dma burst size can be programmed to more efficiently transfer data. ? internal four-word fifo per channel. ? supports 8, 16, and 32-bit wide transactions. ? big-endian and little-endian support. the dma controller defaults to little-endian mode on reset. ? an interrupt to the processor can be generated on a dma completion or when a dma error has occurred. ? raw interrupt status. the dma error and dma count raw interrupt status can be read prior to masking. 7.18.2 spi flash interface (spifi) the spi flash interface allows low-cost serial flash memories to be connected to the arm cortex-m4 processor with little performance penalty compared to parallel flash devices with higher pin count.
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 69 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller after a few commands configure the interface at startup, the enti re flash content is accessible as normal memory using byte, halfword, and word accesses by the processor and/or dma channels. erasure and programmi ng are handled by simple sequences of commands. many serial flash devices use a half-duplex command-driven spi protocol for device setup and initialization and then move to a half -duplex, command-driven 4-bit protocol for normal operation. different serial flash vendo rs and devices accept or require different commands and command fo rmats. spifi provides sufficient flexibility to be compatible with common flash devices and includes extensio ns to help insure compatibility with future devices. 7.18.2.1 features ? interfaces to serial flash me mory in the main memory map. ? supports classic and 4-bit bidirectional serial protocols. ? half-duplex protocol compatible with various vendors and devices. ? data rates of up to 52 mb per second. ? supports dma access. 7.18.3 sd/mmc card interface the sd/mmc card interface support s the following mo des to control: ? secure digital memo ry (sd version 3.0) ? secure digital i/o (sdio version 2.0) ? consumer electronics advanced transport architecture (ce-ata version 1.1) ? multimedia cards (mmc version 4.4) 7.18.4 external memory controller (emc) the lpc4370 emc is a memory controller peripheral offering support for asynchronous static memory devices such as ram, rom, a nd flash. in addition, it can be used as an interface with off-chip memory-mapped devices and peripherals. 7.18.4.1 features ? dynamic memory interface support in cluding single data rate sdram. ? asynchronous static memory device suppor t including ram, rom, and flash, with or without asynchronous page mode. ? low transaction latency. ? read and write buffers to reduce latency and to improve performance. ? 8/16/32 data and 24 address lines wide static memory support. ? 16 bit and 32 bit wide chip select sdram memory support. ? static memory features include: ? asynchronous page mode read ? programmable wait states ? bus turnaround delay ? output enable and write enable delays
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 70 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller ? extended wait ? four chip selects for synchro nous memory and four chip selects for static memory devices. ? power-saving modes dynamically contro l emc_ckeout and emc_clk signals to sdrams. ? dynamic memory self-refresh mode controlled by software. ? controller supports 2048 (a0 to a10), 4096 (a0 to a11), and 8192 (a0 to a12) row address synchronous memory parts. that is typical 512 mb, 256 mb, and 128 mb parts, with 4, 8, 16, or 32 data bits per device. ? separate reset domains allow the for auto-refresh through a chip reset if desired. ? sdram clock can run at full or half the cortex-m4 core frequency. note: synchronous static memory devices (synchronous burst mode) are not supported. 7.18.5 high-speed usb host/device/otg interface (usb0) the usb otg module allows the lpc4370 to co nnect directly to a usb host such as a pc (in device mode) or to a usb device in host mode. 7.18.5.1 features ? contains utmi+ compliant transceiver (phy). ? complies with universal serial bus specification 2.0 . ? complies with usb on-the-go supplement . ? complies with enhanced host controller interface specification . ? supports auto usb 2.0 mode discovery. ? supports all high-speed usb-compliant peripherals. ? supports all full-speed usb-compliant peripherals. ? supports software host ne gotiation protocol (hnp) an d session request protocol (srp) for otg peripherals. ? supports interrupts. ? this module has its own, integrated dma engine. ? usb interface electrical test software included in rom usb stack. 7.18.6 high-speed usb host/device interface with ulpi (usb1) the usb1 interface can operate as a full-speed usb host/device interface or can connect to an external ulpi phy for high-speed operation. 7.18.6.1 features ? complies with universal serial bus specification 2.0 . ? complies with enhanced host controller interface specification . ? supports auto usb 2.0 mode discovery. ? supports all high-speed usb-compliant peripherals if connected to external ulpi phy. ? supports all full-speed usb-compliant peripherals. ? supports interrupts.
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 71 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller ? this module has its own, integrated dma engine. ? usb interface electrical test software included in rom usb stack. 7.18.7 lcd controller remark: the lcd controller is available on the lpc4370fet256 parts. see ta b l e 2 . the lcd controller provides all of the necessary control signals to interface directly to a variety of color and monochrome lcd panels. both stn (single and dual panel) and tft panels can be operated. the display resolution is selectable and can be up to 1024 ? 768 pixels. several color modes are provided, up to a 24-bit true-color non-palettized mode. an on-chip 512-byte color palette allows reducing bus utilizati on (i.e. memory size of the displayed data) while still supporti ng a large number of colors. the lcd interface includes its own dma controlle r to allow it to operate independently of the cpu and other system functions. a built-in fifo acts as a buffer for display data, providing flexibility for system timing. hardware cursor su pport can furthe r reduce the amount of cpu time needed to operate the display. 7.18.7.1 features ? ahb master interface to access frame buffer. ? setup and control via a separate ahb slave interface. ? dual 16-deep programmable 64-bit wide fifos for buffering incoming display data. ? supports single and dual-panel monochrome super twisted nematic (stn) displays with 4-bit or 8-bit interfaces. ? supports single and dual-panel color stn displays. ? supports thin film transi stor (tft) color displays. ? programmable display resolution including, but not limited to: 320 ? 200, 320 ? 240, 640 ? 200, 640 ? 240, 640 ? 480, 800 ? 600, and 1024 ? 768. ? hardware cursor support for single-panel displays. ? 15 gray-level monochrome, 3375 color stn, and 32 k color palettized tft support. ? 1, 2, or 4 bits-per-pixel (bpp) palettized displays for monochrome stn. ? 1, 2, 4, or 8 bpp palettized color displays for color stn and tft. ? 16 bpp true-color non-palettized for color stn and tft. ? 24 bpp true-color non-palettized for color tft. ? programmable timing for different display panels. ? 256 entry, 16-bit palette ram, arranged as a 128 ? 32-bit ram. ? frame, line, and pixel clock signals. ? ac bias signal for stn, data enable signal for tft panels. ? supports little and big-endian, and windows ce data formats. ? lcd panel clock may be generated from the peripheral clock, or from a clock input pin.
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 72 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller 7.18.8 ethernet 7.18.8.1 features ? 10/100 mbit/s ? dma support ? power management remote wake-up frame and magic packet detection ? supports both full-duplex and half-duplex operation ? supports csma/cd protocol for half-duplex operation. ? supports ieee 802.3x flow control for full-duplex operation. ? optional forwarding of received pause co ntrol frames to the user application in full-duplex operation. ? back-pressure support for half-duplex operation. ? automatic transmission of zero-quanta p ause frame on deassertion of flow control input in full-dup lex operation. ? supports ieee1588 time stamping and i eee 1588 advanced time stamping (ieee 1588-2008 v2). 7.19 digital serial peripherals 7.19.1 uart1 the lpc4370 contain one uart with standard transmit and receive data lines, uart1 also provides a full modem control handshak e interface and support for rs-485/9-bit mode allowing both software address detection and automatic address detection using 9-bit mode. uart1 includes a fractional baud rate generator. standard baud rates such as 115200 bd can be achieved with any crystal frequency above 2 mhz. 7.19.1.1 features ? maximum uart data bit rate of 8 mbit/s. ? 16 b receive and transmit fifos. ? register locations conform to 16c550 industry standard. ? receiver fifo trigger points at 1 b, 4 b, 8 b, and 14 b. ? built-in fractional baud rate generator cove ring wide range of baud rates without a need for external crystals of particular values. ? auto baud capabilities and fifo control mechanism that enables software flow control implementation. ? equipped with standard modem interface signals. this module also provides full support for hardware flow control. ? support for rs-485/9-bit /eia-485 mode (uart1). ? dma support.
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 73 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller 7.19.2 usart0/2/3 the lpc4370 contain three usarts. in addition to standard transmit and receive data lines, the usarts support a synchronous mode. the usarts include a fractional baud rate generator. standard baud rates such as 115200 bd can be achieved with any crystal frequency above 2 mhz. 7.19.2.1 features ? maximum uart data bit rate of 8 mbit/s. ? 16 b receive and transmit fifos. ? register locations conform to 16c550 industry standard. ? receiver fifo trigger points at 1 b, 4 b, 8 b, and 14 b. ? built-in fractional baud rate generator cove ring wide range of baud rates without a need for external crystals of particular values. ? auto baud capabilities and fifo control mechanism that enables software flow control implementation. ? support for rs-485/9 -bit/eia-485 mode. ? usart3 includes an irda mode to support infrared communication. ? all usarts have dma support. ? support for synchronous mode at a data bit rate of up to 8 mbit/s. ? smart card mode conforming to iso7816 specification 7.19.3 spi serial i/o controller the lpc4370 contain one spi controller. spi is a full duplex serial interface designed to handle multiple masters and slaves connected to a given bus. only a single master and a single slave can communicate on the interface during a given data transfer. during a data transfer the master always sends 8 bits to 16 bits of data to the slave, and the slave always sends 8 bits to 16 bits of data to the master. 7.19.3.1 features ? maximum spi data bit rate 25 mhz in master and slave modes. ? compliant with spi specification ? synchronous, serial, full duplex communication ? combined spi master and slave ? maximum data bit rate of one eighth of the input clock rate ? 8 bits to 16 bits per transfer 7.19.4 ssp serial i/o controller remark: the lpc4370 contain two ssp controllers. the ssp controller is capable of operation on a spi, 4-wire ssi, or microwire bus. it can interact with multiple masters and slaves on the bus. only a single master and a single slave can communicate on the bus during a given data trans fer. the ssp supports full
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 74 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. in practice, often only one of these data flows carries meaningful data. 7.19.4.1 features ? maximum ssp speed in full-duplex mode of 25 mbit/s; for transmit only 50 mbit/s (master) and 15 mbit/s (slave). ? compatible with motorola spi, 4-wire texas instruments ssi, and national semiconductor microwire buses ? synchronous serial communication ? master or slave operation ? 8-frame fifos for both transmit and receive ? 4-bit to 16-bit frame ? dma transfers supported by gpdma 7.19.5 i 2 c-bus interface remark: the lpc4370 each contain two i 2 c-bus interfaces. the i 2 c-bus is bidirectional for inter-ic contro l using only two wires: a serial clock line (scl) and a serial data line (sda). each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an lcd driver) or a transmitter with the capability to both receive and send information (such as me mory). transmitters and/or receivers can operate in either master or sl ave mode, depending on whether the chip has to initiate a data transfer or is only addressed. the i 2 c is a multi-master bus and can be controlled by more than one bus master connected to it. 7.19.5.1 features ? i 2 c0 is a standard i 2 c compliant bus interface with open-drain pins. i 2 c0 also supports fast mode plus with bit rates up to 1 mbit/s. ? i 2 c1 uses standard i/o pins with bit rates of up to 400 kbit/s (fast i 2 c-bus). ? easy to configure as master, slave, or master/slave. ? programmable clocks allow versatile rate control. ? bidirectional data transfer between masters and slaves. ? multi-master bus (no central master). ? arbitration between simultaneously transmit ting masters without corruption of serial data on the bus. ? serial clock synchronization allows devices with different bit rates to communicate via one serial bus. ? serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. ? the i 2 c-bus can be used for test and diagnostic purposes. ? all i 2 c-bus controllers support multiple address recognition and a bus monitor mode. 7.19.6 i 2 s interface remark: the lpc4370 each contain two i 2 s-bus interfaces.
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 75 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller the i 2 s-bus provides a standard communication interface for digital audio applications. the i 2 s-bus specification defines a 3-wire serial bus using one data line, one clock line, and one word select signal. the basic i 2 s-bus connection has one master, which is always the master, and one slave. the i 2 s-bus interface provides a separate transmit and receive channel, each of which can o perate as either a master or a slave. 7.19.6.1 features ? both i 2 s interfaces have separate input/output channels, each of which can operate in master or slave mode. ? capable of handling 8-bit, 16-bit, and 32-bit word sizes. ? mono and stereo audio data supported. ? the sampling frequency can range from 16 khz to 192 khz (16, 22.05, 32, 44.1, 48, 96, 192) khz. ? support for an audio master clock. ? configurable word select period in master mode (separately for i 2 s-bus input and output). ? two 8-word fifo data buffers are provided, one for transmit and one for receive. ? generates interrupt requests when buffer levels cross a programmable boundary. ? two dma requests for each i 2 s interface, controlled by programmable buffer levels. these are connected to the gpdma block. ? controls include reset, stop and mute options separately for i 2 s-bus input and i 2 s-bus output. 7.19.7 c_can remark: the lpc4370 each contain two c_can controllers. use of c_can controller excludes operation of all other peripherals connected to the same bus bridge. see figure 1 . controller area network (can) is the definition of a high performance communication protocol for serial data communication. the c_ can controller is designed to provide a full implementation of the can protocol accordin g to the can specification version 2.0b. the c_can controller allows to build powerful local networks with low-cost multiplex wiring by supporting distributed real-t ime control with a very hi gh level of reliability. 7.19.7.1 features ? conforms to protocol version 2.0 parts a and b. ? supports bit rate of up to 1 mbit/s. ? supports 32 message objects. ? each message object has its own identifier mask. ? provides programmable fifo mode (concatenation of message objects). ? provides maskable interrupts. ? supports disabled automatic retransmission (dar) mode for time-triggered can applications. ? provides programmable loop-back mode for self-test operation.
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 76 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller 7.20 counter/timers and motor control 7.20.1 general purpose 32-bit timers/external event counters the lpc4370 include four 32-bit timer/counters. the timer/counter is designed to count cycles of the system derived clock or an externally-supplied clock. it can optionally generate interrupts, generate timed dma reques ts, or perform other actions at specified timer values, based on four match registers. each timer/counter also includes two capture inputs to trap the timer value when an input si gnal transitions, optionally generating an interrupt. 7.20.1.1 features ? a 32-bit timer/counter with a programmable 32-bit prescaler. ? counter or timer operation. ? two 32-bit capture channels per timer, that can take a snapshot of the timer value when an input signal transitions. a capture event may also generate an interrupt. ? four 32-bit match registers that allow: ? continuous operation with optional interrupt generation on match. ? stop timer on match with optional interrupt generation. ? reset timer on match with optional interrupt generation. ? up to four external outputs corresponding to match registers, with the following capabilities: ? set low on match. ? set high on match. ? toggle on match. ? do nothing on match. ? up to two match registers can be used to generate timed dma requests. 7.20.2 motor control pwm the motor control pwm is a specialized pwm supporting 3-phase motors and other combinations. feedback inputs are provided to automatically sense rotor position and use that information to ramp speed up or down. an abort input is also provided that causes the pwm to immediately release all motor drive ou tputs. at the same time, the motor control pwm is highly configurable for other genera lized timing, counting, capture, and compare applications. 7.20.3 quadrature encoder interface (qei) a quadrature encoder, also known as a 2-chan nel incremental encoder, converts angular displacement into two pulse signals. by mo nitoring both the number of pulses and the relative phase of the two signals, the user ca n track the position, direction of rotation, and velocity. in addition, a third channel, or index signal, can be used to reset the position counter. the quadrature encoder interface decodes the digital pulses from a quadrature encoder wheel to integrate position over ti me and determine direction of rotation. in addition, the qei can capture the velocity of the encoder wheel.
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 77 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller 7.20.3.1 features ? tracks encoder position. ? increments/decrements depending on direction. ? programmable for 2 ? or 4 ? position counting. ? velocity capture using built-in timer. ? velocity compare function with ?less than? interrupt. ? uses 32-bit registers for position and velocity. ? three position compare registers with interrupts. ? index counter for re volution counting. ? index compare register with interrupts. ? can combine index and position interrupts to produce an interrupt for whole and partial revolution displacement. ? digital filter with prog rammable delays for encoder input signals. ? can accept decoded signal inputs (clk and direction). 7.20.4 repetitive interrupt (ri) timer the repetitive interrupt timer provides a free-r unning 32-bit counter which is compared to a selectable value, generating an interrupt when a match occurs. any bits of the timer/compare can be masked such that they do not contribute to the match detection. the repetitive interrupt timer can be used to create an interrupt that repeats at predetermined intervals. 7.20.4.1 features ? 32-bit counter. counter can be free-running or be reset by a generated interrupt. ? 32-bit compare value. ? 32-bit compare mask. an interrupt is generated when the counter value equals the compare value, after masking. this allows for co mbinations not poss ible with a simple compare. 7.20.5 windowed watchdog timer (wwdt) the purpose of the watchdog is to reset the controller if software fails to periodically service it within a programmable time window. 7.20.5.1 features ? internally resets chip if not periodically reloaded during the programmable time-out period. ? optional windowed operation requires reload to occur between a minimum and maximum time period, both programmable. ? optional warning interrupt can be generated at a programmable time prior to watchdog time-out. ? enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. ? incorrect feed sequence causes reset or interrupt if enabled.
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 78 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller ? flag to indicate watchdog reset. ? programmable 24-bit timer with internal prescaler. ? selectable time period from (t cy(wdclk) ? 256 ? 4) to (t cy(wdclk) ? 2 24 ? 4) in multiples of t cy(wdclk) ? 4. 7.21 analog peripherals 7.21.1 12-bit high-speed analog-to-digital converter (adchs) 7.21.1.1 features ? 12-bit high-speed adc. ? six single-sided input channels or one differential input channel. ? descriptor based conversion sequence for single or multiple inputs. ? integrated 14-bit timer. ? automatic high/low threshold detection. ? power-down mode. ? measurement range of 0 v to 1.2 v. ? 12-bit conversion rate of 80 msamples/s. ? conversion on transition on input pin or various internal signals. ? output fifo with dma support. 7.21.2 10-bit analog-to-digital converter (adc0/1) 7.21.2.1 features ? 10-bit successive approximation analog to digital converter. ? input multiplexing among 8 pins per adc for a total of 16 individual channels. ? power-down mode. ? measurement range 0 to vdda. ? sampling frequency up to 400 ksamples/s. ? burst conversion mode for single or multiple inputs. ? optional conversion on transition on adct rig0 or adctrig1 pi ns, combined timer outputs 8 or 15, or the pwm output mcoa2. ? individual result registers for each a/d channel to reduce interrupt overhead. ? dma support. 7.21.3 digital-to-analog converter (dac) 7.21.3.1 features ? 10-bit resolution ? monotonic by design (resistor string architecture) ? controllable conversion speed ? low power consumption
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 79 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller 7.22 peripherals in the rtc power domain 7.22.1 rtc the real time clock (rtc) is a set of count ers for measuring time when system power is on, and optionally when it is off. it uses very little power when its registers are not being accessed by the cpu, especially reduced power modes. the rtc is clocked by a separate 32 khz oscillator that produces a 1 hz internal time reference. the rtc is powered by its own power supply pin, vbat. 7.22.1.1 features ? measures the passage of time to maintain a calendar and clock. provides seconds, minutes, hours, day of month, month, year, day of week, and day of year. ? ultra-low power design to support batter y powered systems. uses power from the cpu power supply when it is present. ? dedicated battery power supply pin. ? rtc power supply is isolated from the rest of the chip. ? calibration counter allows adjustment to better than ? 1 sec/day with 1 sec resolution. ? periodic interrupts can be generated from increments of any field of the time registers. ? alarm interrupt can be generated for a specific date/time. 7.22.2 alarm timer the alarm timer is a 16-bit timer and counts down at 1 khz from a preset value generating alarms in intervals of up to 1 min. the counter triggers a status bit when it reaches 0x00 and asserts an interrupt if enabled. the alarm timer is part of the rtc power domain and can be battery powered. 7.23 system control 7.23.1 configuration registers (creg) the following settings are controlled in the configuration register block: ? bod trip settings ? oscillator output ? dma-to-peripheral muxing ? ethernet mode ? memory mapping ? timer/usart inputs ? enabling the usb controllers in addition, the creg block contains the pa rt identification and part configuration information. 7.23.2 system control unit (scu) the system control unit determines the function and electrical mode of the digital pins. by default function 0 is selected for all pins with pull-up enabled. for pins that support a
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 80 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller digital and analog function, the adc function select registers in the scu enable the analog function. a separate set of analog i/os for the adcs and the dac as well as most usb pins are located on separate pads and are not controlled through the scu. in addition, the clock delay register for th e sdram emc_clk pins and the registers that select the pin interrupts are located in the scu. 7.23.3 clock generation unit (cgu) the clock generator unit (cgu) generates several base clocks. the cgu outputs are unrelated in frequency and phase and can ha ve different clock s ources within the cgu. one cgu output is routed to the clkout pins. within each clock area there may be multiple branch clocks, which offers very flexible control for power-management purposes. all branch clocks are outputs of one of two clock control units (ccus) and can be controlled independently. branch clocks derived from the same base clock are synchronous in frequency and phase. 7.23.4 internal rc oscillator (irc) the irc is used as the clock source for the wwdt and/or as the clock that drives the plls and subsequently the cpu. the nominal irc frequency is 12 mhz. the irc is trimmed to 1 % accuracy over the entire voltage and temperature range. upon power-up or any chip reset, the lpc4370 use the irc as the clock source. software may later switch to one of the other available clock sources. 7.23.5 pll0usb (for usb0) pll0 is a dedicated pll for the usb0 high-speed controller. pll0 accepts an input clock fr equency from an external osc illator in the r ange of 14 khz to 25 mhz. the input frequency is multiplied up to a high frequency with a current controlled oscillator (cco). the cco operates in the ra nge of 4.3 mhz to 550 mhz. 7.23.6 pll0audio (for audio) the audio pll pll0audio is a general purpose pll with a very small step size. this pll accepts an input clock frequency derived fr om an external oscilla tor or internal irc. the input frequency is multiplied up to a high frequency with a current controlled oscillator (cco). a sigma-delta converter modulates the pll divider ratios to obtain the desired output frequency. the output frequency can be set as a multiple of the sampling frequency f s to 32 ??? f s , 64 ??? f s , 128 ? f s , 256 ? f s , 384 ? f s , 512 ? f s and the sampling frequency f s can range from 16 khz to 192 khz (1 6, 22.05, 32, 44.1, 48, 96,192) khz. many other frequencies are possible as well. 7.23.7 system pll1 the pll1 accepts an input clock frequency from an external oscilla tor in the range of 10 mhz to 25 mhz. the input frequency is multiplied up to a high frequency with a current controlled oscillator (cco ). the multiplier can be an inte ger value from 1 to 32. the cco operates in the range of 156 mhz to 320 mhz, so there is an additional divider in the loop to keep the cco within its frequency range wh ile the pll is providing the desired output frequency. the output divider may be set to divide by 2, 4, 8, or 16 to produce the output
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 81 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller clock. since the minimum output divider value is 2, it is insured that the pll output has a 50 % duty cycle. the pll is turned off and bypassed following a chip reset and may be enabled by software. the program must config ure and activate the pll, wait for the pll to lock, and then connect to the pll as a clock source. the pll settling time is 100 ? s. 7.23.8 reset generation unit (rgu) the rgu allows generation of independent reset signals for individual blocks and peripherals on the lpc4370. 7.23.9 power control the lpc4370 feature several independent powe r domains to control power to the core and the peripherals (see figure 7 ). the rtc and its associated peripherals (the alarm timer, the creg block, the otp controller, the back-up registers, and the event router) are located in the rtc power-domain which can be powered by a battery supply or the main regulator. a power selector switch ensures that the rtc block is always powered on.
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 82 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller 7.23.9.1 memory retention in po wer-down modes ta b l e 6 shows which parts of the sram memory are preserved in sleep mode and the various power-down modes. in addition, all fifo memory contained in the peripheral blocks (usb0/1, lcd, can, ethernet, usart0/2/3, uart) is retained in sleep mode and deep-sleep mode but not in power-down mode and deep-power-down mode. fig 7. power domains real-time clock backup registers reset/wake-up control regulator 32 khz oscillator always-on/rtc power domain main power domain rtcx1 vbat vddreg rtcx2 vddio vss to memories, peripherals, oscillators, plls to cores to i/o pads adc dac otp adc power domain otp power domain usb0 power domain vdda vssa vpp usb0 usb0_vdda3v_driver usb0_vdda3v3 lpc43xx ultra low-power regulator alarm reset wakeup0/1/2/3 to rtc domain peripherals 002aag378 to rtc i/o pads (v ps )
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 83 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller 7.23.9.2 power management controller (pmc) the pmc controls the power to the cores, peripherals, and memories. the lpc4370 support the following power modes in order from highest to lowest power consumption: 1. active mode 2. sleep mode 3. power-down modes: a. deep-sleep mode b. power-down mode c. deep power-down mode active mode and sleep mode apply to the stat e of the core. in a multi-core system, any core can be in active or sleep mode independently of the other core. if the core is in active mode, it is fully operational and can access peripherals and memories as configured by software. if the core is in sleep mode, it receives no clocks, but peripherals and memories can remain running. any core can enter sleep mode from active mode independently of the other cores and while the other cores remain in active mode or are in sleep mode. power-down modes apply to the entire system . in the power-down mo des, all cores and all peripherals except for peripherals in the always-on power domain are shut down. memories can remain powered for retaining memo ry contents as defined by the individual power-down mode. any core in active mode can put the part into one of the three power down modes if the core is enabled to do so. if both the m4 core and the two m0 cores are enabled for power-down, then the system enters power-down only once all three cores have received a wfi or wfe instruction. wake-up from sleep mode is caused by an interrupt or event in the core?s nvic. an interrupt is captured in the nvic and an even t is captured in the event router. both cores can wake up from sleep mode independently of each other. table 6. memory retention mode 128 kb local sram starting at 0x1000 0000 64 kb local sram starting at 0x1008 0000 8 kb local sram starting at 0x1009 0000 16 + 2 kb m0 subsystem sram starting at location 0x1800 0000 64 kb ahb sram starting at 0x2000 0000 256 byte backup registers at 0x4004 1000 (rtc power domain) sleep mode yes yes yes yes yes yes deep-sleep mode yes yes yes yes yes yes power-down mode no no yes no no yes power-down mode with m0sub sram maintained no no yes yes no yes deep power-down mode no no no no no yes
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 84 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller wake-up from the power-down modes, deep-sleep, power-down, and deep power-down, is caused by an event on the wakeup pins or an event from the rtc or alarm timer. when waking up from deep power-down mode, the part resets and attempts to boot. after booting, the m4 core is in active mode and both m0 cores remain in the reset state until the reset is releas ed by software. 7.24 serial wire debug/jtag debug and trace functions are integrated in to the arm cortex-m4. serial wire debug and trace functions are supported in addition to a standard jtag debug and parallel trace functions. the arm cortex-m4 is configured to support up to eight breakpoints and four watch points. the arm cortex-m0 coprocessors support jtag boundary scan only.
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 85 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller 8. limiting values [1] the following applies to the limiting values: a) this product includes circui try designed for the protection of its internal dev ices from the damaging effects of excessive st atic charge. nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) parameters are valid over operating te mperature range unless otherwise specifi ed. all voltages are with respect to v ss unless otherwise noted. c) the limiting values are stress ratings only and operating the pa rt at these values is not recommended and proper operation is not guaranteed. the conditions for functi onal operation are specified in table 10 . [2] including voltage on outputs in 3-state mode. [3] the peak current is limited to 25 times the corresponding maximum current. [4] dependent on package type. [5] human body model: equivalent to dischar ging a 100 pf capacitor through a 1.5 k ? series resistor. table 7. limiting values in accordance with the absolute ma ximum rating system (iec 60134). [1] symbol parameter conditions min max unit v dd(reg)(3v3) regulator supply voltage (3.3 v) on pin vddreg ? 0.5 3.6 v v dd(io) input/output supply voltage on pin vddio ? 0.5 3.6 v v dda(3v3) analog supply voltage (3.3 v) on pin vdda ? 0.5 3.6 v v bat battery supply voltage on pin vbat ? 0.5 3.6 v v prog(pf) polyfuse programming voltage on pin vpp ? 0.5 3.6 v v i input voltage only valid when the v dd(io) ? 2.2 v 5 v tolerant i/o pins [2] ? 0.5 5.5 v adc/dac pins and digital i/o pins configured for an analog function ? 0.5 v dda(3v3) v usb0 pins usb0_dp; usb0_dm;usb0_vbus ? 0.3 5.25 v usb0 pins usb0_id; usb0_rref ? 0.3 3.6 v usb1 pins usb1_dp and usb1_dm ? 0.3 5.25 v i dd supply current per supply pin [3] - 100 ma i ss ground current per ground pin [3] - 100 ma i latch i/o latch-up current ? (0.5v dd(io) ) < v i < (1.5v dd(io) ); t j < 125 ?c - 100 ma t stg storage temperature [4] ? 65 +150 ?c p tot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption -1.5w v esd electrostatic discharge voltage human body model; all pins [5] +2000 v
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 86 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller 9. thermal characteristics the average chip junction temperature, t j ( ? c), can be calculated using the following equation: (1) ? t amb = ambient temperature ( ? c), ? r th(j-a) = the package junction-to-ambient thermal resistance ( ? c/w) ? p d = sum of internal and i/o power dissipation the internal power dissipation is the product of i dd and v dd . the i/o power dissipation of the i/o pins is often small and many times can be negligible. however it can be significant in some applications. t j t amb p d r th j a ? ?? ? ?? += table 8. thermal characteristics v dd = 2.2 v to 3.6 v; t amb = ? ? ? symbol parameter conditions min typ max unit t j(max) maximum junction temperature --125 ? c table 9. thermal resistance value (bga package) symbol parameter conditions thermal resistance in ? c/w 15 % lbga256 tfbga100 r th(j-a) thermal resistance from junction to ambient jedec (4.5 in ? 4 in); still air 29 46 8-layer (4.5 in ? 3 in); still air 24 37 r th(j-c) thermal resistance from junction to case 14 11
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 87 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller 10. static characteristics table 10. static characteristics t amb = ? 40 ? c to +85 ? c, unless otherwise specified. symbol parameter conditions min typ [1] max unit supply pins v dd(io) input/output supply voltage 2.2 - 3.6 v v dd(reg)(3v3) regulator supply voltage (3.3 v) [2] 2.2 - 3.6 v v dda(3v3) analog supply voltage (3.3 v) on pin vdda 2.2 - 3.6 v on pins usb0_vdda3v3_ driver and usb0_vdda3v3 3.0 3.3 3.6 v v bat battery supply voltage [2] 2.2 - 3.6 v v prog(pf) polyfuse programming voltage on pin vpp (for otp) [3] 2.7 - 3.6 v i prog(pf) polyfuse programming current on pin vpp; otp programming time ? 1.6 ms --30ma i dd(reg)(3v3) regulator supply current (3.3 v) active mode; m0 cores in reset; code while(1){} executed from ram; all peripherals disabled; pll1 enabled cclk = 12 mhz [4] -6 . 6-m a cclk = 60 mhz [4] 25.3 - ma cclk = 120 mhz [4] -4 8 . 4-m a cclk = 180 mhz [4] -7 2 . 0-m a cclk = 204 mhz [4] -8 1 . 5-m a i dd(reg)(3v3) regulator supply current (3.3 v) after wfe/wfi instruction executed from ram; all peripherals disabled;m0 cores in reset sleep mode [4] [5] -5 . 0-m a deep-sleep mode [4] -3 0- ? a power-down mode [4] -1 5- ? a power-down mode with m0sub sram retained [4] - 20 - ? a deep power-down mode [4] [6] -0 . 0 3- ? a deep power-down mode; vbat floating [4] -2- ? a i bat battery supply current active mode; v bat = 3.2 v; v dd(reg)(3v3) = 3.6 v. [7] -0 -n a
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 88 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller i bat battery supply current v dd(reg)(3v3) = 3.3 v; v bat = 3.6 v deep-sleep mode [8] -2- ? a power-down mode [8] -2- ? a deep power-down mode [8] -2- ? a i dd(io) i/o supply current deep sleep mode - 1 - ? a power-down mode - 1 - ? a deep power-down mode [9] -0 . 0 5- ? a i dda analog supply current on pin vdda; deep sleep mode [11] -0 . 4- ? a power-down mode [11] -0 . 4- ? a deep power-down mode [11] -0 . 0 0 7- ? a reset pin v ih high-level input voltage [10] 0.8 ? (v ps ? 0.35) -5 . 5v v il low-level input voltage [10] 0 - 0.3 ? (v ps ? 0.1) v v hys hysteresis voltage [10] 0.05 ? (v ps ? 0.35) --v standard i/o pins - normal drive strength c i input capacitance - - 2 pf i ll low-level leakage current v i = 0 v; on-chip pull-up resistor disabled -3-na i lh high-level leakage current v i =v dd(io) ; on-chip pull-down resistor disabled -3-na v i = 5 v --2 0n a i oz off-state output current v o =0v to v dd(io) ; on-chip pull-up/down resistors disabled; absolute value -3-n a v i input voltage pin configured to provide a digital function; v dd(io) ? 2.2 v 0- 5.5v v dd(io) = 0 v 0 - 3.6 v v o output voltage output active 0 - v dd(io) v v ih high-level input voltage 0.7 ? v dd(io) -5 . 5v v il low-level input voltage 0 - 0.3 ? v dd(io) v v hys hysteresis voltage 0.1 ? v dd(io) --v table 10. static characteristics ?continued t amb = ? 40 ? c to +85 ? c, unless otherwise specified. symbol parameter conditions min typ [1] max unit
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 89 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller v oh high-level output voltage i oh = ? 6 ma v dd(io) ? 0.4 --v v ol low-level output voltage i ol = 6 m a --0 . 4v i oh high-level output current v oh =v dd(io) ? 0.4 v ? 6--ma i ol low-level output current v ol = 0 . 4 v 6--m a i ohs high-level short-circuit output current drive high; connected to ground [12] --8 6 . 5m a i ols low-level short-circuit output current drive low; connected to v dd(io) [12] --7 6 . 5m a i pd pull-down current v i =5 v [14] [15] [16] -9 3- ? a i pu pull-up current v i =0v [14] [15] [16] - ? 62 - ? a v dd(io) lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 90 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller i pd pull-down current v i =v dd(io) [14] [15] [16] -6 2- ? a i pu pull-up current v i =0v [14] [15] [16] - ? 62 - ? a v dd(io) lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 91 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller i ll low-level leakage current v i = 0 v; on-chip pull-up resistor disabled -3-na i lh high-level leakage current v i =v dd(io) ; on-chip pull-down resistor disabled -3-na v i = 5 v --2 0n a i oz off-state output current v o =0v to v dd(io) ; on-chip pull-up/down resistors disabled; absolute value -3-n a v i input voltage pin configured to provide a digital function; v dd(io) ? 2.2 v 0 - 5.5 v v dd(io) = 0 v 0 - 3.6 v v o output voltage output active 0 - v dd(io) v v ih high-level input voltage 0.7 ? v dd(io) -5 . 5v v il low-level input voltage 0 - 0.3 ? v dd(io) v v hys hysteresis voltage 0.1 ? v dd(io) --v v oh high-level output voltage i oh = ? 8 ma v dd(io) ? 0.4 --v v ol low-level output voltage i ol = 8 m a --0 . 4v i oh high-level output current v oh =v dd(io) ? 0.4 v ? 8--ma i ol low-level output current v ol = 0 . 4 v 8--m a i ohs high-level short-circuit output current drive high; connected to ground [12] --8 6m a i ols low-level short-circuit output current drive low; connected to v dd(io) [12] --7 6m a i pd pull-down current v i =v dd(io) [14] [15] [16] -6 2- ? a i pu pull-up current v i =0v [14] [15] [16] - ? 62 - ? a v dd(io) lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 92 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller v hys hysteresis voltage 0.1 ? v dd(io) --v v ol low-level output voltage i ols = 3 m a --0 . 4v i li input leakage current v i =v dd(io) [13] -4 . 5- ? a v i = 5 v --1 0 ? a oscillator pins v i(xtal1) input voltage on pin xtal1 ? 0.5 - 1.2 v v o(xtal2) output voltage on pin xtal2 ? 0.5 - 1.2 v c io input/output capacitance [17] --0 . 8p f usb0 pins [18] v i input voltage on pins usb0_dp; usb0_dm; usb0_vbus v dd(io) ? 2.2 v 0 - 5.25 v v dd(io) = 0 v 0 - 3.6 v r pd pull-down resistance on pin usb0_vbus 48 64 80 k ? v ic common-mode input voltage high-speed mode ? 50 200 500 mv full-speed/low-speed mode 800 - 2500 mv chirp mode ? 50 - 600 mv v i(dif) differential input voltage 100 400 1100 mv usb1 pins (usb1_dp/usb1_dm) [18] i oz off-state output current 0v lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 93 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller [1] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. [2] dynamic characteristics fo r peripherals are provided for v dd(reg)(3v) ? 2.7 v. [3] pin vpp should either be not connected (when otp does not need to be programmed) or tied to pins vddio and vddreg to ensure the same ramp-up time for both supply voltages. [4] v dd(reg)(3v3) = 3.3 v; v dd(io) = 3.3 v; t amb =25 ? c. [5] pll1 disabled; irc running; cclk = 12 mhz. [6] v bat = 3.6 v. [7] v dd(io) = v dda = 3.6 v; over entire frequency range cclk = 12 mhz to 180 mhz. [8] on pin vbat; t amb =25 ? c. [9] v dd(reg)(3v3) = 3.3 v; v dd(io) = 3.3 v. input leakage increases when v dd(io) is floating or grounded. it is recommended to keep v dd(reg)(3v3) and v dd(io) powered in deep power-down mode. [10] v ps corresponds to the output of the power switch (see figure 7 ) which is determined by the greater of v bat and v dd(reg)(3v3) . [11] v dda(3v3) = 3.3 v; t amb =25 ? c. [12] allowed as long as the current limit does not exceed the maximum current allowed by the device. [13] to v ss . [14] the values specified are simulated and absolute values. [15] the weak pull-up resist or is connected to the v dd(io) rail and pulls up the i/o pin to the v dd(io) level. [16] the input cell disables the weak pull-up re sistor when the applied input voltage exceeds v dd(io) . [17] the parameter value specified is a simulated value excluding bond capacitance. [18] for usb operation 3.0 v ? v dd((io) ? 3.6 v. guaranteed by design. [19] v dd(io) present. [20] includes external resistors of 33 ?? 1 % on d+ and d ? . v oh high-level output voltage (driven) for low-/full-speed r l of 15 k ? to gnd 2.8 - 3.5 v c trans transceiver capacitance pin to gnd - - 20 pf z drv driver output impedance for driver which is not high-speed capable with 33 ? series resistor; steady state drive [20] 36 - 44.1 ? table 10. static characteristics ?continued t amb = ? 40 ? c to +85 ? c, unless otherwise specified. symbol parameter conditions min typ [1] max unit
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 94 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller 10.1 power consumption conditions: t amb = 25 ? c; active mode entered executing code wh ile(1){} from sram; m0 cores in reset; internal pull-up resistors disabled; pll1 en abled; irc enabled; all per ipherals disabled; all peripheral clocks disabled. fig 8. typical supply current versus regulator supply voltage v dd(reg)(3v3) in active mode conditions: v dd(reg)(3v3) = 3.3 v, active mode entered executing code while(1){} from sram;m0 cores in reset; internal pull-up resistors di sabled; pll1 enabled; irc enabled; all peripherals disabled; all peripheral clocks disabled. fig 9. typical supply current versus temperature in active mode 002aah611 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 0 20 40 60 80 100 v dd(reg)(3v3) (v) idd(reg)(3v3) idd(reg)(3v3) i dd(reg)(3v3) (ma) (ma) (ma) 12 mhz 12 mhz 12 mhz 60 mhz 60 mhz 60 mhz 120 mhz 120 mhz 120 mhz 180 mhz 180 mhz 180 mhz 204 mhz 204 mhz 204 mhz 002aah612 -40 -15 10 35 60 85 0 20 40 60 80 100 temperature (c) idd(reg)(3v3) idd(reg)(3v3) i dd(reg)(3v3) (ma) (ma) (ma) 12 mhz 12 mhz 12 mhz 60 mhz 60 mhz 60 mhz 120 mhz 120 mhz 120 mhz 180 mhz 180 mhz 180 mhz 204 mhz 204 mhz 204 mhz
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 95 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller conditions: v dd(reg)(3v3) = 3.3 v; active mode entered executing code while(1){} from sram;m0 cores in reset; internal pull-up resistors di sabled; pll1 enabled; irc enabled; all peripherals disabled; all peripheral clocks disabled. fig 10. typical supply current versus frequency in active mode conditions: v dd(reg)(3v3) = 3.3 v; m0 cores in reset; internal pull-up resistors disabled; pll1 enabled; irc enabled; all peripherals disabled; all per ipheral clocks disabled; core clock cclk = 12 mhz. fig 11. typical supply current ver sus temperature in sleep mode 002aah613 12 36 60 84 108 132 156 180 204 0 20 40 60 80 100 cclk frequency (mhz) idd(reg)(3v3) idd(reg)(3v3) i dd(reg)(3v3) (ma) (ma) (ma) 85 c 85 c 85 c 25 c 25 c 25 c -40 c -40 c -40 c 002aah153 -40 -15 10 35 60 85 0 2 4 6 8 10 temperature (c) i dd(reg)(3v3) ( ( (ma)
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 96 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller conditions: v dd(reg)(3v3) = 3.3 v; v bat floating; v dd(io) = 3.3 v. fig 12. typical supply current versu s temperature in deep-sleep mode conditions: v dd(reg)(3v3) = 3.3 v; v bat floating; v dd(io) = 3.3 v. fig 13. typical supply current versu s temperature in power-down mode 002aah154 -40 -15 10 35 60 85 0 60 120 180 240 300 temperature (c) i dd(reg)(3v3) )( )( (a) 002aah155 -40 -15 10 35 60 85 0 10 20 30 40 50 temperature (c) i dd(reg)(3v3) )( )( (a)
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 97 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller conditions: v dd(reg)(3v3) = 3.3 v; v bat floating; v dd(io) = 3.3 v. fig 14. typical supply current versus temperature in deep power-down mode conditions: v dd(reg)(3v3) = 3.0 v; cclk = 12 mhz. fig 15. typical battery supply current in active mode 002aah156 -40 -15 10 35 60 85 0 2 4 6 8 10 temperature (c) i dd(reg)(3v3) dd(reg (a) 002aah150 -0.4 -0.2 0 0.2 0.4 0.6 0 20 40 60 80 v bat - v dd(reg)(3v3) (v) i bat (a)
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 98 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller 10.2 peripheral power consumption the typical power consumption at t = 25 ? c for each individual peripheral is measured as follows: 1. enable all branch clocks and measure the current i dd(reg)(3v3) . 2. disable the branch clock to the peripheral to be measured and keep all other branch clocks enabled. 3. calculate the difference between measurement 1 and 2. the result is the peripheral power consumption. conditions: v dd(reg)(3v3) , v dd(io) floating. fig 16. typical battery supply versus temperature in deep power-down mode 002aah157 -40 -15 10 35 60 85 0 2 4 6 8 10 temperature (c) i bat (a) 3.6 v 3.0 v 2.2 v v bat = table 11. peripheral power consumption peripheral branch clock i dd(reg)(3v3) in ma branch clock frequency = 48 mhz branch clock frequency = 96 mhz m0 subsystem core clk_periph_core 2.4 4.8 m0 coprocessor clk_m4_m0app 3.3 6.6 i2c1 clk_apb3_i2c1 0.01 0.02 i2c0 clk_apb1_i2c0 0.02 0.01 dac clk_apb3_dac 0.01 0.02 adc0 (10-bit) clk_apb3_adc0 0.05 0.05 adc1 (10-bit) clk_apb3_adc1 0.04 0.04 can0 clk_apb3_can0 0.17 0.17 can1 clk_apb1_can1 0.17 0.17 motocon clk_apb1_motocon 0.05 0.05 i2s clk_apb1_i2s 0.11 0.11 spifi clk_spifi, clk_m4_spifi 0.95 1.85
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 99 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller gpio clk_m4_gpio 0.66 1.31 lcd clk_m4_lcd 0.85 1.72 ethernet clk_m4_ethernet 1.05 2.09 uart0 clk_m4_uart0, clk_apb0_uart0 0.3 0.38 uart1 clk_m4_uart1, clk_apb0_uart1 0.27 0.48 uart2 clk_m4_uart2, clk_apb2_uart2 0.27 0.47 uart3 clk_m4_usart3, clk_apb2_uart3 0.29 0.49 timer0 clk_m4_timer0 0.07 0.14 timer1 clk_m4_timer1 0.07 0.14 timer2 clk_m4_timer2 0.07 0.15 timer3 clk_m4_timer3 0.06 0.11 sdio clk_m4_sdio, clk_sdio 0.79 1.37 sct clk_m4_sct 0.52 1.05 ssp0 clk_m4_ssp0, clk_apb0_ssp0 0.12 0.21 ssp1 clk_m4_ssp1, clk_apb2_ssp1 0.15 0.28 dma clk_m4_dma 1.88 3.71 wwdt clk_m4_wwdt 0.05 0.08 qei clk_m4_qei 0.33 0.68 usb0 clk_m4_usb0, clk_usb0 1.46 3.32 usb1 clk_m4_usb1, clk_usb1 2.83 5.03 ritimer clk_m4_ritimer 0.04 0.08 emc clk_m4_emc, clk_m4_emc_div 3.6 6.97 scu clk_m4_scu 0.09 0.23 creg clk_m4_creg 0.37 0.72 sgpio clk_periph_sgpio 0.1 0.17 spi clk_spi 0.07 0.11 table 11. peripheral power consumption peripheral branch clock i dd(reg)(3v3) in ma branch clock frequency = 48 mhz branch clock frequency = 96 mhz
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 100 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller 10.3 bod static characteristics [1] interrupt and reset levels are selected by writing to the bodlv1/2 bits in the control register crege0, see the lpc43xx user manual . table 12. peripheral power consumption 12-bit adchs peripheral branch clock i dd(reg)(3v3) in ma branch clock frequency = 39 mhz branch clock frequency = 78 mhz conditions adchs (12-bit adc) clk_adchs, clk_m4_adch 1.1 2.3 peripheral power consumption; no adc conversions adchs (12-bit adc) clk_adchs, clk_m4_adch 28.5 41.6 peripheral power consumption; adc converting samples at clk_adchs frequency table 13. bod static characteristics [1] t amb =25 ? c; simulated values for nominal processing. symbol parameter conditions min typ max unit v th threshold voltage interrupt level 0 assertion - 2.75 - v de-assertion - 2.92 - v interrupt level 1 assertion - 2.85 - v de-assertion - 3.00 - v interrupt level 2 assertion - 2.95 - v de-assertion - 3.12 - v interrupt level 3 assertion - 3.05 - v de-assertion - 3.19 - v reset level 0 assertion - 1.70 - v de-assertion - 1.85 - v reset level 1 assertion - 1.80 - v de-assertion - 1.95 - v reset level 2 assertion - 1.90 - v de-assertion - 2.05 - v reset level 3 assertion - 2.00 - v de-assertion - 2.15 - v
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 101 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller 10.4 electrical pi n characteristics conditions: v dd(reg)(3v3) =v dd(io) =3.3v. fig 17. normal-drive pins; typical low level output current i ol versus low level output voltage v ol conditions: v dd(reg)(3v3) =v dd(io) =3.3v. fig 18. normal-drive pins; typica l high level output voltage v oh versus hgh level output current i oh 002aah030 0 0.1 0.2 0.3 0.4 0.5 0.6 0 3 6 9 12 15 v ol (v) i ol (ma) -40 c 25 c 85 c i oh (ma) 0 36 24 12 002aah039 2.8 2.4 3.2 3.6 v oh (v) 2.0 t = 85 c 25 c -40 c
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 102 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller conditions: v dd(reg)(3v3) =v dd(io) = 3.3 v; normal-drive; ehd = 0x0. conditions: v dd(reg)(3v3) =v dd(io) =3.3v; medium-drive; ehd = 0x1. conditions: v dd(reg)(3v3) =v dd(io) = 3.3 v; high-drive; ehd = 0x2. conditions: v dd(reg)(3v3) =v dd(io) = 3.3 v; ultra high-drive; ehd = 0x3. fig 19. high-drive pins; typical low level output current i ol versus low level output voltage v ol 002aah040 0 0.1 0.2 0.3 0.4 0.5 0.6 0 3 6 9 12 15 v ol (v) i ol (ma) -40 c 25 c 85 c 002aah041 0 0.1 0.2 0.3 0.4 0.5 0.6 0 5 10 15 20 25 v ol (v) i ol (ma) -40 c 25 c 85 c 002aah043 0 0.1 0.2 0.3 0.4 0.5 0.6 0 8 16 24 32 40 v ol (v) i ol (ma) -40 c 25 c 85 c 002aah044 0 0.1 0.2 0.3 0.4 0.5 0.6 0 15 30 45 60 v ol (v) i ol (ma) -40 c 25 c 85 c
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 103 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller conditions: v dd(reg)(3v3) =v dd(io) = 3.3 v; normal-drive; ehd = 0x0. conditions: v dd(reg)(3v3) =v dd(io) =3.3v; medium-drive; ehd = 0x1. conditions: v dd(reg)(3v3) =v dd(io) = 3.3 v; high-drive; ehd = 0x2. conditions: v dd(reg)(3v3) =v dd(io) = 3.3 v; ultra high-drive; ehd = 0x3. fig 20. high-drive pins; typical high level output voltage v oh versus hgh level output current i oh 002aah047 i oh (ma) 024 16 8 2.0 3.2 2.8 2.4 3.6 v oh (v) -40 c 25 c 85 c 002aah048 i oh (ma) 048 32 16 2.0 3.2 2.8 2.4 3.6 v oh (v) -40 c 25 c 85 c 002aah049 i oh (ma) 096 64 32 2.0 3.2 2.8 2.4 3.6 v oh (v) -40 c 25 c 85 c 002aah050 i oh (ma) 0 120 80 40 2.0 3.2 2.8 2.4 3.6 v oh (v) -40 c 25 c 85 c
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 104 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller conditions: v dd(io)) = 3.3 v. simulated values. values at t = 25 ? c are typical values. values at t= ?40 ? c correspond to minimum values. fig 21. typical pull-up current i pu versus input voltage v i conditions: v dd(io)) = 3.3 v. simulated values. values at t = 25 ? c are typical values. values at t= ?40 ? c correspond to maximum values. fig 22. typical pull-down current i pd versus input voltage v i v i (v) 0 5 4 23 1 002aag625 -40 -20 -60 0 +20 i pu (a) -80 t = 25 c -40 c v i (v) 0 5 4 23 1 002aag626 60 30 90 120 i pd (a) 0 t =25 c -40 c
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 105 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller 11. dynamic characteristics 11.1 wake-up times [1] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. [2] t cy(clk) = 1/cclk with cclk = cpu clock frequency. 11.2 external clock for o scillator in slave mode remark: the input voltage on the xtal1/2 pins must be ? 1.2 v (see table 10 ). for connecting the oscillator to the xtal pins, also see section 13.2 and section 13.4 . [1] parameters are valid over operating temp erature range unless otherwise specified. table 14. dynamic characteristic: wake-up from deep-sleep, power-down, and deep power-down modes t amb = ? 40 ? c to +85 ? c symbol parameter conditions min typ [1] max unit t wake wake-up time from sleep mode [2] 3 ? t cy(clk) 5 ? t cy(clk) -ns from deep-sleep and power-down mode 12 51 - ? s from deep power-down mode - 250 - ? s after reset - 250 - ? s table 15. dynamic characteristic: external clock t amb = ? 40 ? c to +85 ? c; v dd(io) over specified ranges. [1] symbol parameter conditions min max unit f osc oscillator frequency 1 25 mhz t cy(clk) clock cycle time 40 1000 ns t chcx clock high time t cy(clk) ? 0.4 t cy(clk) ? 0.6 ns t clcx clock low time t cy(clk) ? 0.4 t cy(clk) ? 0.6 ns fig 23. external clock timing (with an amplitude of at least v i(rms) = 200 mv) t clcx t chcx t cy(clk) 002aag698
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 106 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller 11.3 crystal oscillator [1] parameters are valid over operating temp erature range unless otherwise specified. [2] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. [3] indicates rms period jitter. [4] pll-induced jitter is not included. [5] select hf = 0 in the xtal_osc_ctrl register. [6] select hf = 1 in the xtal_osc_ctrl register. 11.4 irc oscillator [1] parameters are valid over operating te mperature range unless otherwise specified. [2] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. 11.5 rtc oscillator [1] parameters are valid over operating te mperature range unless otherwise specified. [2] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. table 16. dynamic characteristic: oscillator t amb = ? 40 ? c to +85 ? c; v dd(io) over specified ranges; 2.2 v ? v dd(reg)(3v3) ? 3.6 v. [1] symbol parameter conditions min typ [2] max unit low-frequency mode (1 mhz - 20 mhz) [5] t jit(per) period jitter time 5 mhz crystal [3] [4] - 13.2 - ps 10 mhz crystal - 6.6 - ps 15 mhz crystal - 4.8 - ps high-frequency mode (20 mhz - 25 mhz) [6] t jit(per) period jitter time 20 mhz crystal [3] [4] -4.3- ps 25 mhz crystal - 3.7 - ps table 17. dynamic characteristic: irc oscillator t amb = ? 40 ? c to +85 ? c; 2.2 v ? v dd(reg)(3v3) ? 3.6 v. [1] symbol parameter conditions min typ [2] max unit f osc(rc) internal rc oscillator frequency - 11.88 12.0 12.12 mhz table 18. dynamic characte ristic: rtc oscillator t amb = ? 40 ? c to +85 ? c; 2.2 v ? v dd(reg)(3v3) ? 3.6 v or 2.2 v ? v bat ? 3.6 v [1] ; typical c rtcx1/2 = 20 pf; also see section 13.3 . symbol parameter conditions min typ [2] max unit f i(rtc) rtc input frequency - - 32.768 - khz i dd(rtc) rtc supply current 280 800 na
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 107 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller 11.6 i 2 c-bus [1] parameters are valid over oper ating temperature range unless otherwise specified. see the i 2 c-bus specification um10204 for details. [2] thd;dat is the data hold time that is measured from the fa lling edge of scl; applies to data in transmission and the acknowl edge. [3] a device must internally provide a hold time of at least 300 ns for the sda signal (with respect to the v ih (min) of the scl signal) to bridge the undefined region of the falling edge of scl. [4] c b = total capacitance of one bus line in pf. if mixed with hs-mode devices, faster fall times are allowed. [5] the maximum t f for the sda and scl bus lines is specified at 300 ns. the maximum fall time for the sda output stage t f is specified at 250 ns. this allows series protection re sistors to be connected in between the sda and the scl pins and the sda/scl bus lines without exceeding the maximum specified t f . [6] in fast-mode plus, fall time is specified the same for bot h output stage and bus timing. if se ries resistors are used, desig ners should allow for this when c onsidering bus timing. [7] the maximum t hd;dat could be 3.45 ? s and 0.9 ? s for standard-mode and fast-mode but must be less than the maximum of t vd;dat or t vd;ack by a transition time. this maximum must only be met if the device does not stretch the low period (t low ) of the scl signal. if the clock stretches the scl, the data must be valid by the set-up time before it releases the clock. [8] tsu;dat is the data set-up time that is measured with respec t to the rising edge of scl; applies to data in transmission and the acknowledge. [9] a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system but the requirement t su;dat = 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stre tch the low period of the scl signal, it must output the next data bit to the sda line t r(max) + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the scl line is released. al so the acknowledge timing must meet this set-up time. table 19. dynamic characteristic: i 2 c-bus pins t amb = ? 40 ? c to +85 ? c; 2.2 v ? v dd(reg)(3v3) ? 3.6 v. [1] symbol parameter conditions min max unit f scl scl clock frequency standard-mode 0 100 khz fast-mode 0 400 khz fast-mode plus 0 1 mhz t f fall time [3] [4] [5] [6] of both sda and scl signals standard-mode - 300 ns fast-mode 20 + 0.1 ? c b 300 ns fast-mode plus - 120 ns t low low period of the scl clock standard-mode 4.7 - ? s fast-mode 1.3 - ? s fast-mode plus 0.5 - ? s t high high period of the scl clock standard-mode 4.0 - ? s fast-mode 0.6 - ? s fast-mode plus 0.26 - ? s t hd;dat data hold time [2] [3] [7] standard-mode 0 - ? s fast-mode 0 - ? s fast-mode plus 0 - ? s t su;dat data set-up time [8] [9] standard-mode 250 - ns fast-mode 100 - ns fast-mode plus 50 - ns
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 108 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller 11.7 i 2 s-bus interface [1] clock to the i 2 s-bus interface base_apb1_clk = 150 mhz; peripheral clock to the i 2 s-bus interface pclk = base_apb1_clk / 12. i 2 s clock cycle time t cy(clk) = 79.2 ns; corresponds to the sck signal in the i 2 s-bus specification . fig 24. i 2 c-bus pins clock timing 002aaf425 t f 70 % 30 % sda t f 70 % 30 % s 70 % 30 % 70 % 30 % t hd;dat scl 1 / f scl 70 % 30 % 70 % 30 % t vd;dat t high t low t su;dat table 20. dynamic characteristics: i 2 s-bus interface pins t amb =25 ? c; 2.2 v ? v dd(reg)(3v3) ? 3.6 v; 2.7 v ? v dd(io) ? 3.6 v; c l = 20 pf. conditions and data refer to i2s0 and i2s1 pins. simulated values. symbol parameter conditions min typ max unit common to input and output t r rise time - 4 - ns t f fall time - 4 - ns t wh pulse width high on pins i2sx_tx_sck and i2sx_rx_sck 36 - - ns t wl pulse width low on pins i2sx_tx_sck and i2sx_rx_sck 36 - - ns output t v(q) data output valid time on pin i2sx_tx_sda [1] -4.4- ns on pin i2sx_tx_ws - 4.3 - ns input t su(d) data input set-up time on pin i2sx_rx_sda [1] -0- ns on pin i2sx_rx_ws 0.20 ns t h(d) data input hold time on pin i2sx_rx_sda [1] -3.7- ns on pin i2sx_rx_ws - 3.9 - ns
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 109 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller 11.8 usart interface fig 25. i 2 s-bus timing (transmit) fig 26. i 2 s-bus timing (receive) 002aag497 i2sx_tx_sck i2sx_tx_sda i2sx_tx_ws t cy(clk) t f t r t wh t wl t v(q) t v(q) 002aag498 t cy(clk) t f t r t wh t su(d) t h(d) t su(d) t su(d) t wl i2sx_rx_sck i2sx_rx_sda i2sx_rx_ws table 21. dynamic characte ristics: usart interface t amb =25 ? c; 2.2 v ? v dd(reg)(3v3) ? 3.6 v; 2.7 v ? v dd(io) ? 3.6 v; c l = 20 pf. simulated values. symbol parameter conditions min typ max unit t cy(clk) clock cycle time on pins ux_uclk - 0.1 - ? s output t v(q) data output valid time on pin ux_txd - 6.5 - ns
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 110 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller 11.9 ssp interface [1] t cy(clk) = (sspclkdiv ? (1 + scr) ? cpsdvsr) / f main . the clock cycle time deriv ed from the spi bit rate t cy(clk) is a function of the main clock frequency f main , the ssp peripheral clock divider (sspclkdiv), the ssp scr parameter (specified in the ssp0cr0 register), and the ssp cpsdvsr parameter (spec ified in the ssp clock prescale register). [2] t cy(clk) = 12 ? t cy(pclk) . table 22. dynamic characteristics: ssp pins in spi mode t amb =25 ? c; 2.2 v ? v dd(reg)(3v3) ? 3.6 v; 2.7 v ? v dd(io) ? 3.6 v. simulated values. symbol parameter conditions min typ max unit t cy(clk) clock cycle time full-duplex mode [1] -4 0 -n s when only transmitting -2 0 -n s ssp master t ds data set-up time in spi mode 13.3 - - ns t dh data hold time in spi mode ? 3.5 - - ns t v(q) data output valid time in spi mode - - 6.0 ns t h(q) data output hold time in spi mode - - 0 ns ssp slave t cy(pclk) pclk cycle time 10 ns t cy(clk) clock cycle time [2] 120 - - ns t ds data set-up time in spi mode - 10.5 - ns t dh data hold time in spi mode - 1 - ns t v(q) data output valid time in spi mode - 4.0 - ns t h(q) data output hold time in spi mode - 0.2 - ns
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 111 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller 11.10 spi interface [1] t cy(clk) = 8/base_spi_clk. tcy(pclk) = 1/base_spi_clk. 11.11 ssp/spi timing diagrams table 23. dynamic characteristics: spi t amb = ? 40 ? c to +85 ? c; 2.2 v ? v dd(reg)(3v3) ? 3.6 v; 2.7 v ? v dd(io) ? 3.6 v. simulated values. symbol parameter conditions min typ max unit t cy(pclk) pclk cycle time 5 ns t cy(clk) clock cycle time [1] 40 - - ns master t ds data set-up time 7.2 - - ns t dh data hold time 0 - - ns t v(q) data output valid time - - 3.7 ns t h(q) data output hold time - - 1.2 ns slave t ds data set-up time 1.2 - - ns t dh data hold time 3 x t cy(pclk) + 0.54 - - ns t v(q) data output valid time - - 3 x t cy(pclk) + 9.7 ns t h(q) data output hold time - - 2 x t cy(pclk) + 7.1 ns fig 27. ssp master timing in spi mode sck (cpol = 0) mosi miso t cy(clk) t ds t dh t v(q) data valid data valid t h(q) sck (cpol = 1) data valid data valid mosi miso t ds t dh data valid data valid t h(q) data valid data valid t v(q) cpha = 1 cpha = 0 002aae829
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 112 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller fig 28. ssp slave timing in spi mode sck (cpol = 0) mosi miso t cy(clk) t ds t dh t v(q) data valid data valid t h(q) sck (cpol = 1) data valid data valid mosi miso t ds t dh t v(q) data valid data valid t h(q) data valid data valid cpha = 1 cpha = 0 002aae830
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 113 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller 11.12 spifi 11.13 sgpio timing the following considerations apply to sgpio timing: ? sgpio input signals are synchronized by the internal clock sgpio_clock. to guarantee that no samples are missed, all input signals should have a duration of at least one sgpio_clock cycle plus the set-up and hold times. ? when an external clock input is used to generate output data, synchronization causes a latency of at least one sgpio_clock cycle. the maximum output data rate is one output every two sgpio_clock cycles. ? synchronization also causes a latency of one sgpio_clock cycle when sampling several inputs. this may cause inputs with ve ry similar timings to be sampled with a difference of one sgpio_clock cycle. table 24. dynamic characteristics: spifi t amb = ? 40 ? c to 85 ? c; 2.2 v ? v dd(reg)(3v3) ? 3.6 v; 2.7 v ? v dd(io) ? 3.6 v. c l = 10 pf. simulated values. symbol parameter min max unit t cy(clk) clock cycle time 9.6 - ns t ds data set-up time 3.4 - ns t dh data hold time ? -ns t v(q) data output valid time - 8 ns t h(q) data output hold time 5 - ns fig 29. spifi timing spifi_sck spifi data out spifi data in t cy(clk) t ds t dh t v(q) data valid data valid t h(q) data valid data valid 002aah409
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 114 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller [1] sgpio_clock is the internally generated sgpio clock. t sgpio = 1/f sgpio_clock . table 25. dynamic ch aracteristics: sgpio t amb = ? 40 ? c to +85 ? c; 2.2 v ? v dd(reg)(3v3) ? 3.6 v; 2.7 v ? v dd(io) ? 3.6 v. simulated values. symbol parameter conditions min typ max unit t su(d) data input set-up time 2 - - ns t h(d) data input hold time [1] t sgpio + 2 - - ns t su(d) data input set-up time sampled by sgpio_clock [1] t sgpio + 2 - - ns t h(d) data input hold time sampled by sgpio_clock [1] t sgpio + 2 - - ns t v(q) data output valid time [1] - - 2 x t sgpio ns t h(q) data output hold time [1] t sgpio -n s t v(q) data output valid time sampled by sgpio_clock [1] -3 - 3 ns t h(q) data output hold time sampled by sgpio_clock [1] -3 - 3 ns fig 30. sgpio timing sgpio_clock din clkinext sync(clkinext) = clkini sync(din) dout clkout dini dini dqi t h(d) t su(d) t h(q) t v(q) 002aah668
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 115 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller 11.14 external memory interface table 26. dynamic characteristics: static asynchronous external memory interface c l = 22 pf for emc_dn c l = 20 pf for all others; t amb = ? 40 ? c to 85 ? c; 2.2 v ? v dd(reg)(3v3) ? 3.6 v; 2.7 v ? v dd(io) ? 3.6 v; values guar anteed by design. timing parameters are gi ven for single memory access cycles. in a normal read operation, the emc changes the address while cs is asserted which results in multiple memory accesses. symbol parameter [1] conditions min typ max unit read cycle parameters t cslav cs low to address valid time ? 3.1 - 1.6 ns t csloel cs low to oe low time [2] ? 0.6 + t cy(clk) ? waitoen - 1.3 + t cy(clk) ? waitoen ns t cslblsl cs low to bls low time pb = 1 ? 0.7 - 1.8 ns t oeloeh oe low to oe high time [2] ? 0.6 + (waitrd ? waitoen + 1) ? t cy(clk) - ? 0.4 + (waitrd ? waitoen + 1) ? t cy(clk) ns t am memory access time - - ? 16 + (waitrd ? waitoen +1) ? t cy(clk) ns t h(d) data input hold time ? 16 - - ns t cshblsh cs high to bls high time pb = 1 ? 0.4 - 1.9 ns t cshoeh cs high to oe high time ? 0.4 - 1.4 ns t oehanv oe high to address invalid pb = 1 ? 2.0 - 2.6 ns t csheor cs high to end of read time [3] ? 2.0 - 0 ns t cslsor cs low to start of read time [4] 0- 1 . 8n s write cycle parameters t cslav cs low to address valid time ? 3.1 - 1.6 ns t csldv cs low to data valid time ? 3.1 - 1.5 ns t cslwel cs low to we low time pb = 1 ? 1.5 - 0.2 ns t cslblsl cs low to bls low time pb = 1 ? 0.7 - 1.8 ns t welweh we low to we high time pb = 1 [2] ? 0.6 + (waitwr ? waitwen + 1) ? t cy(clk) - ? 0.4 + (waitwr ? waitwen + 1) ? t cy(clk) ns t wehdnv we high to data invalid time pb = 1 [2] ? 0.9 + t cy(clk) - 2.3 + t cy(clk) ns t weheow we high to end of write time pb = 1 [2] [5] ? 0.4 + t cy(clk) - ? 0.3 + t cy(clk) ns t cslblsl cs low to bls low pb = 0 ? 0.7 - 1.8 ns t blslblsh bls low to bls high time pb = 0 [2] ? 0.9 + (waitwr ? waitwen + 1) ? t cy(clk) - ? 0.1 + (waitwr ? waitwen + 1) ? t cy(clk) ns
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 116 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller [1] parameters specified for 40 % of v dd(io) for rising edges and 60 % of v dd(io) for falling edges. [2] t cy(clk) = 1/cclk (see lpc43xx user manual). [3] end of read (eor): longest of t cshoeh , t oehanv , t cshblsh . [4] start of read (sor): longest of t cslav , t csloel , t cslblsl . [5] end of write (eow): earliest of address not valid or emc_blsn high. t blsheow bls high to end of write time pb = 0 [2] [5] ? 1.9 + t cy(clk) - ? 0.5 + t cy(clk) ns t blshdnv bls high to data invalid time pb = 0 [2] ? 2.5 + t cy(clk) - 1.4 + t cy(clk) ns t csheow cs high to end of write time [5] ? 2.0 - 0 ns t blshdnv bls high to data invalid time pb = 1 ? 2.5 - 1.4 ns t wehanv we high to address invalid time pb = 1 ? 0.9 + t cy(clk) - 2.4 + t cy(clk) ns table 26. dynamic characteristics: static asynchronous external memory interface ?continued c l = 22 pf for emc_dn c l = 20 pf for all others; t amb = ? 40 ? c to 85 ? c; 2.2 v ? v dd(reg)(3v3) ? 3.6 v; 2.7 v ? v dd(io) ? 3.6 v; values guar anteed by design. timing parameters are gi ven for single memory access cycles. in a normal read operation, the emc changes the address while cs is asserted which results in multiple memory accesses. symbol parameter [1] conditions min typ max unit fig 31. external static memory read/write access (pb = 0) t csldv t cslblsl t csheow t blsheow t cslav eor sor eow emc_an emc_csn emc_oe emc_blsn emc_we emc_dn 002aag699 t cshoeh t oehanv t csheor t am t cslsor t oeloeh t csloel t cslav t h(d) t blslblsh t blshdnv
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 117 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller fig 32. external static memory read/write access (pb = 1) emc_an t cslav t cslblsl emc_csn emc_oe emc_blsn emc_we t cslsor t csldv t am t h(d) eor sor eow emc_dn t cslwel t welweh t weheow 002aag700 t cslblsl t cslav t csloel t oeloeh t cshoeh t oehanv t cshblsh t csheor t csheow t wehdnv t blshdnv
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 118 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller [1] program the emc_clkn delay values in the emcdelayclk register (see the lpc43xx user manual ). the delay values must be the same for all sdra m clocks emc_clkn: clk0_delay = clk1_delay = clk2_delay = clk3_delay. table 27. dynamic characteristics: dynamic external memory interface simulated data over temper ature and process range; c l = 10 pf for emc_dycsn , emc_ras , emc_cas , emc_we , emc_an; c l = 9 pf for emc_dn; c l = 5 pf for emc_dqmoutn , emc_clkn, emc_ckeoutn ; t amb = ? 40 ? c to 85 ? c; 2.2 v ? v dd(reg)(3v3) ? 3.6 v; v dd(io) =3.3 v ? 10 %; rd = 1 (see lpc43xx user manual); emc_clkn delays clk0_delay = clk1_delay = clk2_delay = clk3_delay = 0. symbol parameter min typ max unit t cy(clk) clock cycle time 8.4 - - ns common to read and write cycles t d(dycsv) dycs delay time - 3.1 + 0.5 ? t cy(clk) 5.1 + 0.5 ? t cy(clk) ns t h(dycs) dycs hold time 0.3 + 0.5 ? t cy(clk) 0.9 + 0.5 ? t cy(clk) -n s t d(rasv) row address strobe valid delay time - 3.1 + 0.5 ? t cy(clk) 4.9 + 0.5 ? t cy(clk) ns t h(ras) row address strobe hold time 0.5 + 0.5 ? t cy(clk) 1.1 + 0.5 ? t cy(clk) -n s t d(casv) column address strobe va lid delay time - 2.9 + 0.5 ? t cy(clk) 4.6 + 0.5 ? t cy(clk) ns t h(cas) column address strobe hold time 0.3 + 0.5 ? t cy(clk) 0.9 + 0.5 ? t cy(clk) -n s t d(wev) we valid delay time - 3.2 + 0.5 ? t cy(clk) 5.9 + 0.5 ? t cy(clk) ns t h(we) we hold time 1.3 + 0.5 ? t cy(clk) 1.4 + 0.5 ? t cy(clk) -n s t d(dqmoutv) dqmout valid delay time - 3.1 + 0.5 ? t cy(clk) 5.0 + 0.5 ? t cy(clk) ns t h(dqmout) dqmout hold time 0.2 + 0.5 ? t cy(clk) 0.8 + 0.5 ? t cy(clk) -n s t d(av) address valid delay time - 3.8 + 0.5 ? t cy(clk) 6.3 + 0.5 ? t cy(clk) ns t h(a) address hold time 0.3 + 0.5 ? t cy(clk) 0.9 + 0.5 ? t cy(clk) -n s t d(ckeoutv) ckeout valid delay time - 3.1 + 0.5 ? t cy(clk) 5.1 + 0.5 ? t cy(clk) ns t h(ckeout) ckeout hold time 0.5 ? t cy(clk) 0.7 + 0.5 ? t cy(clk) -n s read cycle parameters t su(d) data input set-up time ? 1.5 ? 0.5 - ns t h(d) data input hold time - 0.8 2.2 ns write cycle parameters t d(qv) data output valid delay time - 3.8 + 0.5 ? t cy(clk) 6.2 + 0.5 ? t cy(clk) ns t h(q) data output hold time 0.5 ? t cy(clk) 0.7 + 0.5 ? t cy(clk) -n s table 28. dynamic characteristics: dynamic external memory interface; emc_clk[3:0] delay values t amb = ? 40 ? c to 85 ? c; v dd(io) =3.3 v ? 10 %; 2.2 v ? v dd(reg)(3v3) ? 3.6 v. symbol parameter conditions min typ max unit t d delay time delay value clkn_delay = 0 [1] 0.0 0.0 0.0 ns clkn_delay = 1 [1] 0.4 0.5 0.8 ns clkn_delay = 2 [1] 0.7 1.0 1.7 ns clkn_delay = 3 [1] 1.1 1.6 2.5 ns clkn_delay = 4 [1] 1.4 2.0 3.3 ns clkn_delay = 5 [1] 1.7 2.6 4.1 ns clkn_delay = 6 [1] 2.1 3.1 4.9 ns clkn_delay = 7 [1] 2.5 3.6 5.8 ns
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 119 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller for the programmable emc_clk[3:0] clock delays clkn_delay, see table 28 . remark: for sdram operation, set clk0_delay = clk1_delay = clk2_delay = clk3_delay in the emcdelayclk register. fig 33. sdram timing 002aag703 t cy(clk) emc_clkn delay = 0 emc_clkn delay > 0 emc_dycsn, emc_ras, emc_cas, emc_we, emc_ckeoutn, emc_a[22:0], emc_dqmoutn t h(q) t h(q) - t d t h(d) t su(d) t h(d) t su(d) emc_d[31:0] write emc_d[31:0] read; delay = 0 emc_d[31:0] read; delay > 0 t h(x) - t d t d(xv) - t d t d(qv) - t d t d(qv) t h(x) t d(xv) emc_clkn delay t d ; programmable clkn_delay
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 120 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller 11.15 usb interface [1] characterized but not implemented as production test. guaranteed by design. table 29. dynamic characteristics: usb0 and usb1 pins (full-speed) c l = 50 pf; r pu = 1.5 k ? on d+ to v dd(io) ; 3.0 v ? v dd(io) ? 3.6 v. symbol parameter conditions min typ max unit t r rise time 10 % to 90 % 8.5 - 13.8 ns t f fall time 10 % to 90 % 7.7 - 13.7 ns t frfm differential rise and fall time matching t r /t f --1 0 9% v crs output signal crossover voltage 1.3 - 2.0 v t feopt source se0 interval of eop see figure 34 160 - 175 ns t fdeop source jitter for differential transition to se0 transition see figure 34 ? 2-+5ns t jr1 receiver jitter to next transition ? 18.5 - +18.5 ns t jr2 receiver jitter for paired transitions 10 % to 90 % ? 9-+9ns t eopr1 eop width at receiver must reject as eop; see figure 34 [1] 40 --ns t eopr2 eop width at receiver must accept as eop; see figure 34 [1] 82 --ns fig 34. differential da ta-to-eop transition skew and eop width 002aab561 t period differential data lines crossover point source eop width: t feopt receiver eop width: t eopr1 , t eopr2 crossover point extended differential data to se0/eop skew n t period + t fdeop
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 121 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller [1] characterized but not implemented as production test. [2] total average power consumption. [3] the driver is active only 20 % of the time. 11.16 ethernet table 30. static characte ristics: usb0 phy pins [1] symbol parameter conditions min typ max unit high-speed mode p cons power consumption [2] -68- mw i dda(3v3) analog supply current (3.3 v) on pin usb0_vdda3v3_driver; total supply current [3] -18- ma during transmit - 31 - ma during receive - 14 - ma with driver tri-stated - 14 - ma i ddd digital supply current - 7 - ma full-speed/low-speed mode p cons power consumption [2] -15- mw i dda(3v3) analog supply current (3.3 v) on pin usb0_vdda3v3_driver; total supply current - 3.5 - ma during transmit - 5 - ma during receive - 3 - ma with driver tri-stated - 3 - ma i ddd digital supply current - 3 - ma suspend mode i dda(3v3) analog supply current (3.3 v) - 24 - ? a with driver tri-stated - 24 - ? a with otg functionality enabled - 3 - ma i ddd digital supply current - 30 - ? a vbus detector outputs v th threshold voltage for vbus valid 4.4 - - v for session end 0.2 - 0.8 v for a valid 0.8 - 2 v for b valid 2 - 4 v v hys hysteresis voltage for session end - 150 10 mv a valid - 200 10 mv b valid - 200 10 mv table 31. dynamic charac teristics: ethernet t amb = ? 40 ? c to 85 ? c; 2.2 v ? v dd(reg)(3v3) ? 3.6 v; 2.7 v ? v dd(io) ? 3.6 v. values guaranteed by design. symbol parameter conditions min max unit rmii mode f clk clock frequency for enet_rx_clk [1] -50mhz ? clk clock duty cycle [1] 50 50 %
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 122 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller [1] output drivers can drive a load ? 25 pf accommodating over 12 inch of pcb trace and the input capacitance of the receiving device. [2] timing values are given from the point at which the cl ock signal waveform crosses 1.4 v to the valid input or output level. t su set-up time for enet _txdn, enet_tx_en, enet_rxdn, enet_rx_er, enet_rx_dv [1] [2] 4- ns t h hold time for enet_txdn, enet_tx_en, enet_rxdn, enet_rx_er, enet_rx_dv [1] [2] 2- ns mii mode f clk clock frequency for enet_tx_clk [1] - 25 mhz ? clk clock duty cycle [1] 50 50 % t su set-up time for enet _txdn, enet_tx_en, enet_tx_er [1] [2] 4- ns t h hold time for enet_txdn, enet_tx_en, enet_tx_er [1] [2] 2- ns f clk clock frequency for enet_rx_clk [1] - 25 mhz ? clk clock duty cycle [1] 50 50 % t su set-up time for enet _rxdn, enet_rx_er, enet_rx_dv [1] [2] 4- ns t h hold time for enet_r xdn, enet_rx_er, enet_rx_dv [1] [2] 2- ns fig 35. ethernet timing table 31. dynamic charac teristics: ethernet t amb = ? 40 ? c to 85 ? c; 2.2 v ? v dd(reg)(3v3) ? 3.6 v; 2.7 v ? v dd(io) ? 3.6 v. values guaranteed by design. symbol parameter conditions min max unit 002aag210 t h t su enet_rx_clk enet_tx_clk enet_rxd[n] enet_rx_dv enet_rx_er enet_txd[n] enet_tx_en enet_tx_er
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 123 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller 11.17 sd/mmc 11.18 lcd table 32. dynamic characteristics: sd/mmc t amb = ? 40 ? c to 85 ? c, 2.2 v ? v dd(reg)(3v3) ? 3.6 v; 2.7 v ? v dd(io) ? 3.6 v, c l = 20 pf. simulated values. sample_delay = 0x8, drv_delay = 0xf in the sddelay register (see the lpc18xx user manual um10430). symbol parameter conditions min max unit f clk clock frequency on pin sd_clk; data transfer mode 52 mhz t r rise time 0.5 2 ns t f fall time 0.5 2 ns t su(d) data input set-up time on pins sd_datn as inputs 6 - ns on pins sd_cmd as inputs 7 - ns t h(d) data input hold time on pins sd_datn as inputs -1 - ns on pins sd_cmd as inputs ? 1ns t d(qv) data output valid delay time on pins sd_datn as outputs - 17 ns on pins sd_cmd as outputs - 18 ns t h(q) data output hold time on pins sd_datn as outputs 4 - ns on pins sd_cmd as outputs 4 - ns fig 36. sd/mmc timing 002aag204 sd_clk sd_datn (o) sd_datn (i) t d(qv) t h(d) t su(d) t cy(clk) t h(q) sd_cmd (o) sd_cmd (i) table 33. dynamic characteristics: lcd t amb =25 ? c; 2.2 v ? v dd(reg)(3v3) ? 3.6 v; 2.7 v ? v dd(io) ? 3.6 v; c l = 20 pf. simulated values. symbol parameter conditions min typ max unit f clk clock frequency on pin lcd_dclk - 50 - mhz t d(qv) data output valid delay time -17ns t h(q) data output hold time 8.5 - ns
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 124 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller 12. adc/dac electrical characteristics [1] f in = signal input frequency. the bias current is programmable. hi gher bias current allows for a higher adc conversion frequency a t higher power consumption. table 34. 12-bit adc characteristics v dda(3v3) over specified ranges; t amb = ? 40 ? c to +85 ? c; unless otherwise specified. symbol parameter conditions min typ max unit v dc dc input common mode level 0.1 0.5 0.9 v c in input capacitance single ended - 4.5 - pf r i input resistance single ended; per selected positive or negative input pin -5 - k ? v i(range) input voltage range different ial, peak-to-peak 0.72 0.8 0.88 v f c(adc) adc conversion frequency 12-bit resolution - - 80 msamples/s f c(adc) = 10 msamples/s; f in = 1 mhz; bias curren t bits crs[3:0] = 0000 [1] inl integral non-linearity - ? 1.1 - lsb dnl differential non-linearity - ? 0.7 - lsb enob effective number of bits - 10.4 - - snr signal-to-noise ratio - 64.0 - db thd total harmonic distortion - -73 - db sfdr spurious free dynamic range -80 - db hd2 second harmonic distortion --84 - db hd3 third harmonic distortion - -75 - db f c(adc) = 60 msamples/s; f in = 1 mhz; bias current bits crs[3:0] = 0011 [1] inl integral non-linearity - ? 1.2 - lsb dnl differential non-linearity - ? 0.7 - lsb enob effective number of bits - 10.1 - - snr signal-to-noise ratio - 63 - db thd total harmonic distortion - -72 - db sfdr spurious free dynamic range -75 - db hd2 second harmonic distortion --79 - db hd3 third harmonic distortion - -75 - db
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 125 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller [1] the adc is monotonic, there are no missing codes. [2] the differential linearity error (e d ) is the difference between the actual step width and the ideal step width. see figure 37 . [3] the integral non-linearity (e l(adj) ) is the peak difference between the center of the st eps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. see figure 37 . [4] the offset error (e o ) is the absolute difference between the straight line which fits the actual cu rve and the straight line which fits the ideal curve. see figure 37 . [5] the gain error (e g ) is the relative difference in percent between the straight line fitting the actual transfe r curve after removing offset error, and the straight line which fits the ideal transfer curve. see figure 37 . [6] the absolute error (e t ) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated adc and the ideal transfer curve. see figure 37 . [7] t amb = 25 ? c; maximum sampling frequency f s = 4.5 mhz and analog input capacitance c ia = 2 pf. [8] input resistance r i depends on the sampling frequency fs: r i = 2 k ? + 1 / (f s ? c ia ). table 35. 10-bit adc characteristics v dda(3v3) over specified ranges; t amb = ? 40 ? c to +85 ? c; adc frequency 4.5 mhz; unless otherwise specified. symbol parameter conditions min typ max unit v ia analog input voltage 0 - v dda(3v3) v c ia analog input capacitance -- 2 pf e d differential linearity error [1] [2] - ? 0.8 - lsb - ? 1.0 - lsb e l(adj) integral non-linearity [3] - ? 0.8 - lsb - ? 1.5 - lsb e o offset error [4] - ? 0.15 - lsb - ? 0.15 - lsb e g gain error [5] - ? 0.3 - % - ? 0.35 - % e t absolute error [6] - ? 3- lsb - ? 4- lsb r vsi voltage source interface resistance see figure 38 -- 1/(7 ? f clk(adc) ? c ia ) k? r i input resistance [7] [8] -- 1.2 m ? f clk(adc) adc clock frequency - - 4.5 mhz f c(adc) adc conversion frequency 10-bit resolution; 11 clock cycles - - 400 ksamples/s 2-bit resolution; 3 clock cycles 1.5 msamples/s
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 126 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller (1) example of an actual transfer curve. (2) the ideal transfer curve. (3) differential linearity error (e d ). (4) integral non-linearity (e l(adj) ). (5) center of a step of the actual transfer curve. (6) v dda refers to v dda(3v3) on pin vdda and v ssa to analog ground on pin vssa. fig 37. 10-bit adc characteristics 002aaf959 1023 1022 1021 1020 1019 (2) (1) 1024 1018 1019 1020 1021 1022 1023 7 123456 7 6 5 4 3 2 1 0 1018 (5) (4) (3) 1 lsb (ideal) code out v dda(3v3) ? v ssa 1024 offset error e o gain error e g offset error e o v ia (lsb ideal ) 1 lsb =
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 127 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller [1] in the dac cr register, bit bias = 0 (see the lpc43xx user manual ). [2] settling time is calculated within 1/2 lsb of the final value. rs ? 1/((7 ? f clk(adc) ? c ia ) ? 2 k ? fig 38. adc interface to pins lpc43xx adc0_n/adc1_n c ia = 2 pf r vsi r s v ss v ext 002aag704 adc comparator 2 k (analog pin) 2.2 k (multiplexed pin) table 36. dac characteristics v dda(3v3) over specified ranges; t amb = ? 40 ? c to +85 ? c; unless otherwise specified symbol parameter conditions min typ max unit e d differential linearity error 2.7 v ? v dda(3v3) ? 3.6 v [1] - ? 0.8 - lsb 2.2 v ? v dda(3v3) < 2.7 v - ? 1.0 - lsb e l(adj) integral non-linearity code = 0 to 975 2.7 v ? v dda(3v3) ? 3.6 v [1] - ? 1.0 - lsb 2.2 v ? v dda(3v3) < 2.7 v - ? 1.5 - lsb e o offset error 2.7 v ? v dda(3v3) ? 3.6 v [1] - ? 0.8 - lsb 2.2 v ? v dda(3v3) < 2.7 v - ? 1.0 - lsb e g gain error 2.7 v ? v dda(3v3) ? 3.6 v [1] - ? 0.3 - % 2.2 v ? v dda(3v3) < 2.7 v - ? 1.0 - % c l load capacitance - - 200 pf r l load resistance 1 - - k ? t s settling time [1] 0.4 ? s
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 128 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller 13. application information 13.1 lcd panel signal usage table 37. lcd panel connections for stn single panel mode external pin 4-bit mono stn single panel 8-bit mono stn single panel color stn single panel lpc43xx pin used lcd function lpc43xx pin used lcd function lpc43xx pin used lcd function lcd_vd[23:8] - - - - - - lcd_vd7 - - p8_4 ud[7] p8_4 ud[7] lcd_vd6 - - p8_5 ud[6] p8_5 ud[6] lcd_vd5 - - p8_6 ud[5] p8_6 ud[5] lcd_vd4 - - p8_7 ud[4] p8_7 ud[4] lcd_vd3 p4_2 ud[3] p4_2 ud[3] p4_2 ud[3] lcd_vd2 p4_3 ud[2] p4_3 ud[2] p4_3 ud[2] lcd_vd1 p4_4 ud[1] p4_4 ud[1] p4_4 ud[1] lcd_vd0 p4_1 ud[0] p4_1 ud[0] p4_1 ud[0] lcd_lp p7_6 lcdlp p7_6 lcdlp p7_6 lcdlp lcd_enab/ lcdm p4_6 lcdenab/ lcdm p4_6 lcdenab/ lcdm p4_6 lcdenab/ lcdm lcd_fp p4_5 lcdfp p4_5 lcdfp p4_5 lcdfp lcd_dclk p4_7 lcddclk p4_7 lcddclk p4_7 lcddclk lcd_le p7_0 lcdle p7_0 lcdle p7_0 lcdle lcd_pwr p7_7 cdpwr p7_7 lcdpwr p7_7 lcdpwr gp_clkin pf_4 lcdclkin pf_4 lcdclkin pf_4 lcdclkin table 38. lcd panel connections for stn dual panel mode external pin 4-bit mono stn dual panel 8-bit mono stn dual panel color stn dual panel lpc43xx pin used lcd function lpc43xx pin used lcd function lpc43xx pin used lcd function lcd_vd[23:16] - - - - - - lcd_vd15 - - pb_4 l d[7] pb_4 ld[7] lcd_vd14 - - pb_5 l d[6] pb_5 ld[6] lcd_vd13 - - pb_6 l d[5] pb_6 ld[5] lcd_vd12 - - p8_3 ld[4] p8_3 ld[4] lcd_vd11 p4_9 ld[3] p4_9 ld[3] p4_9 ld[3] lcd_vd10 p4_10 ld[2] p4_10 ld[2] p4_10 ld[2] lcd_vd9 p4_8 ld[1] p4_8 ld[1] p4_8 ld[1] lcd_vd8 p7_5 ld[0] p7_5 ld[0] p7_5 ld[0] lcd_vd7 - - ud[7] p8_4 ud[7] lcd_vd6 - - p8_5 ud[6] p8_5 ud[6] lcd_vd5 - - p8_6 ud[5] p8_6 ud[5] lcd_vd4 - - p8_7 ud[4] p8_7 ud[4] lcd_vd3 p4_2 ud[3] p4_2 ud[3] p4_2 ud[3]
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 129 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller lcd_vd2 p4_3 ud[2] p4_3 ud[2] p4_3 ud[2] lcd_vd1 p4_4 ud[1] p4_4 ud[1] p4_4 ud[1] lcd_vd0 p4_1 ud[0] p4_1 ud[0] p4_1 ud[0] lcd_lp p7_6 lcdlp p7_6 lcdlp p7_6 lcdlp lcd_enab/ lcdm p4_6 lcdenab/ lcdm p4_6 lcdenab/ lcdm p4_6 lcdenab/ lcdm lcd_fp p4_5 lcdfp p4_5 lcdfp p4_5 lcdfp lcd_dclk p4_7 lcddclk p4_7 lcddclk p4_7 lcddclk lcd_le p7_0 lcdle p7_0 lcdle p7_0 lcdle lcd_pwr p7_7 lcdpwr p7_7 lcdpwr p7_7 lcdpwr gp_clkin pf_4 lcdclkin pf_4 lcdclkin pf_4 lcdclkin table 38. lcd panel connections for stn dual panel mode external pin 4-bit mono stn dual panel 8-bit mono stn dual panel color stn dual panel lpc43xx pin used lcd function lpc43xx pin used lcd function lpc43xx pin used lcd function table 39. lcd panel connections for tft panels external pin tft 12 bit (4:4:4 mode) tft 16 bit (5:6:5 mode) tft 16 bit (1 :5:5:5 mode) tft 24 bit lpc43xx pin used lcd function lpc43xx pin used lcd function lpc43xx pin used lcd function lpc43xx pin used lcd function lcd_vd23 pb_0 blue3 pb_0 blue4 pb_0 blue4 blue7 lcd_vd22 pb_1 blue2 pb_1 blue3 pb_1 blue3 blue6 lcd_vd21 pb_2 blue1 pb_2 blue2 pb_2 blue2 blue5 lcd_vd20 pb_3 blue0 pb_3 blue1 pb_3 blue1 blue4 lcd_vd19 - - p7_1 blue0 p7_1 blue0 blue3 lcd_vd18 - - - - p7_2 intensity blue2 lcd_vd17 - - - - - - p7_3 blue1 lcd_vd16 - - - - - - p7_4 blue0 lcd_vd15 pb_4 green3 pb_4 gr een5 pb_4 green4 pb_4 green7 lcd_vd14 pb_5 green2 pb_5 gr een4 pb_5 green3 pb_5 green6 lcd_vd13 pb_6 green1 pb_6 gr een3 pb_6 green2 pb_6 green5 lcd_vd12 p8_3 green0 p8_3 green2 p8_3 green1 p8_3 green4 lcd_vd11 - - p4_9 green1 p4_9 green0 p4_9 green3 lcd_vd10 - - p4_10 green0 p4_10 intensity p4_10 green2 lcd_vd9 - - - - - - p4_8 green1 lcd_vd8 - - - - - - p7_5 green0 lcd_vd7 p8_4 red3 p8_4 red4 p8_4 red4 p8_4 red7 lcd_vd6 p8_5 red2 p8_5 red3 p8_5 red3 p8_5 red6 lcd_vd5 p8_6 red1 p8_6 red2 p8_6 red2 p8_6 red5 lcd_vd4 p8_7 red0 p8_7 red1 p8_7 red1 p8_7 red4 lcd_vd3 - - p4_2 red0 p4_2 red0 p4_2 red3 lcd_vd2 - - - - p4_3 intensity p4_3 red2 lcd_vd1 - - - - - - p4_4 red1
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 130 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller 13.2 crystal oscillator the crystal oscillator is controlled by t he xtal_osc_ctrl register in the cgu (see lpc43xx user manual ). the crystal oscillator operates at frequencies of 1 mhz to 25 mhz. this frequency can be boosted to a higher frequency, up to the ma ximum cpu operating frequency, by the pll. the oscillator can operate in one of two modes: slave mode and oscillation mode. ? in slave mode the input clock signal should be coupled by means of a capacitor of 100 pf (c c in figure 39 ), with an amplitude of at le ast 200 mv (rms). the xtal2 pin in this configuration can be left unconnected. ? external components and models used in oscillation mode are shown in figure 40 , and in ta b l e 4 0 and table 41 . since the feedback resistance is integrated on chip, only a crystal and the capacitances c x1 and c x2 need to be connected externally in case of fundamental mode osc illation (the fundam ental frequency is represented by l, c l and r s ). capacitance c p in figure 40 represents the parallel package capacitance and should not be larger than 7 pf. parameters f c , c l , r s and c p are supplied by the crystal manufacturer. lcd_vd0 - - - - - - p4_1 red0 lcd_lp p7_6 lcdlp p7_6 lcdlp p7_6 lcdlp p7_6 lcdlp lcd_enab /lcdm p4_6 lcdenab/ lcdm p4_6 lcdenab/ lcdm p4_6 lcdenab/ lcdm p4_6 lcdenab/ lcdm lcd_fp p4_5 lcdfp p4_5 lcdfp p4_5 lcdfp p4_5 lcdfp lcd_dclk p4_7 lcddclk p4_7 lcddclk p4_7 lcddclk p4_7 lcddclk lcd_le p7_0 lcdle p7_0 lcdle p7_0 lcdle p7_0 lcdle lcd_pwr p7_7 lcdpwr p7_7 lcdpwr p7_7 lcdpwr p7_7 lcdpwr gp_clkin pf_4 lcdclkin pf_4 lcdclkin pf_4 lcdclkin pf_4 lcdclkin table 39. lcd panel connections for tft panels external pin tft 12 bit (4:4:4 mode) tft 16 bit (5:6:5 mode) tft 16 bit (1 :5:5:5 mode) tft 24 bit lpc43xx pin used lcd function lpc43xx pin used lcd function lpc43xx pin used lcd function lpc43xx pin used lcd function table 40. recommended values for c x1/x2 in oscillation mode (crystal and external components parameters) low frequency mode fundamental oscillation frequency maximum crystal series resistance r s external load capacitors c x1 , c x2 2 mhz < 200 ? 33 pf, 33 pf < 200 ? 39 pf, 39 pf < 200 ? 56 pf, 56 pf 4 mhz < 200 ? 18 pf, 18 pf < 200 ? 39 pf, 39 pf < 200 ? 56 pf, 56 pf 8 mhz < 200 ? 18 pf, 18 pf < 200 ? 39 pf, 39 pf
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 131 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller 12 mhz < 160 ? 18 pf, 18 pf < 160 ? 39 pf, 39 pf 16 mhz < 120 ? 18 pf, 18 pf < 80 ? 33 pf, 33 pf 20 mhz <100 ? 18 pf, 18 pf < 80 ? 33 pf, 33 pf table 41. recommended values for c x1/x2 in oscillation mode (crystal and external components parameters) high frequency mode fundamental oscillation frequency maximum crystal series resistance r s external load capacitors c x1 , c x2 15 mhz < 80 ? 18 pf, 18 pf 20 mhz < 80 ? 39 pf, 39 pf < 100 ? 47 pf, 47 pf fig 39. slave mode operation of the on-chip oscillator fig 40. oscillator modes with external crystal model used for c x1 /c x2 evaluation table 40. recommended values for c x1/x2 in oscillation mode (crystal and external components parameters) low frequency mode fundamental oscillation frequency maximum crystal series resistance r s external load capacitors c x1 , c x2 lpc43xx xtal1 c i 100 pf c g 002aag379 002aag380 lpc43xx xtal1 xtal2 c x2 c x1 xtal = c l c p r s l
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 132 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller 13.3 rtc oscillator in the rtc oscillator circuit, only the crystal (xtal) and the capacitances c rtcx1 and c rtcx2 need to be connected externally. typical capacitance values for c rtcx1 and c rtcx2 are c rtcx1/2 = 20 (typical) ? 4 pf. an external clock can be connected to rtcx 1 if rtcx2 is left open. the recommended amplitude of the clock signal is v i(rms) = 100 mv to 200 mv with a coupling capacitance of 5 pf to 10 pf. 13.4 xtal and rtcx printed circui t board (pcb) layout guidelines connect the crystal on the pcb as close as possi ble to the oscillator input and output pins of the chip. take care that the load capacitors c x1 , c x2 , and c x3 in case of third overtone crystal usage have a common ground plane. al so connect the external components to the ground plain. to keep the noise coupled in via the pcb as small as possible, make loops and parasitics as small as possible. choose smaller values of c x1 and c x2 if parasitics increase in the pcb layout. 13.5 standard i/o pi n configuration figure 42 shows the possible pin modes for standard i/o pins with analog input function: ? digital output driver enabled/disabled ? digital input: pull-up enabled/disabled ? digital input: pull-down enabled/disabled ? digital input: repeater mode enabled/disabled ? digital input: input buffer enabled/disabled ? analog input the default configuration for standard i/o pi ns is input with pull-up enabled. the weak mos devices provide a drive capability equiva lent to pull-up and pull-down resistors. fig 41. rtc 32 khz oscillator circuit 002aah148 lpc43xx rtcx1 rtcx2 c rtcx2 c rtcx1 xtal
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 133 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller 13.6 reset pin configuration the glitch filter rejects pul ses of typical 12 ns width. fig 42. standard i/o pin configuration with analog input slew rate bit ehs pull-up enable bit epun pull-down enable bit epd glitch filter analog i/o esd esd pin vddio vssio input buffer enable bit ezi filter select bit zif data input to core data output from core enable output driver 002aah028 fig 43. reset pin configuration v ss reset 002aag702 v ps v ps v ps r pu esd esd 20 ns rc glitch filter pin
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 134 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller 13.7 minimizing interference betwee n digital signals and 12-bit adc signals to reduce interference from digital signals to the high-speed 12-bit adc inputs, do not configure digital pins that are pinned out cl ose to the adc signals as outputs when using the 12-bit adc. for the bga256 package, the pins with interfering signals are shown in ta b l e 4 2 . 13.8 12-bit adchs input selection the high-speed, 12-bit adchs operates with an in ternally generated 1.2 v power supply. the input range for an adc channel is 800 mv (peak-to-peak) in a band from 0 v to 1.2 v. the input range vin_pos is defined by vin_pos = vin_neg +/- 400 mv where vin_neg can be either generated internally or supplied by the external pin adchs_neg. the internally generated reference voltage is vin_neg = 500 mv making the allowed input voltage vin_pos on any adc channel 100 mv ? vin_pos ? 900 mv. see figure 44 . table 42. 12-bit adc signal inte rferences for bga256 package 12-bit adc signal lbga256 ball interfering pins lbga256 ball adchs_0 e3 p4_3, pc_0 c2, d4 adchs_1 c3 p4_1, p8_0, pc_0 a1, e5, d4 adchs_2 a4 pf_10, pf_11 a3, a2 adchs_3 a5 pf_9, pf_10 d6, a3 adchs_4 c6 p7_7, pb_6 b6, a6 adchs_5 b3 pf_11 a2 adchs_neg b5 p7_7, pf_8 b6, e6 fig 44. adchs input range vin_pos 0 -2048 +2047 adc out input range vin_neg - 400 mv vin_neg vin_neg + 400 mv aaa-009653
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 135 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller the allowed input range for vin_neg, if supplied externally on pin adchs_neg, is 350 mv ? vin_neg ? 900 mv. see figure 45 . for the internally generated negative reference voltage vin_neg = 500 mv, one of the following circuits are recommended for the adc channel input: 1. inverting single-ended with gain = 1 or for input range 0 v to 3.3 v 2. non-inverting single-ended with gain = 1 3. non-inverting singe-ended for input range 0 v to 3.3 v fig 45. positive input voltage as a function of the externally supplied negative voltage vin_neg (on pin adchs_neg) vin_neg (mv) vin_pos (mv) 350 850 400 800 0 750 1200 800 400 450 aaa-009654
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 136 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller 13.8.1 inverting single-ended circuit for the inverting single-ended circuit only o ne op-amp is needed. a 1.24 v shunt voltage reference is used for creating an offset voltag e of 450 mv. the disadvantage is that the signal output of the circuit is inverted. howeve r, this can be easily solved in software by subtracting the adc output from 4095, which is the maximum value of the 12-bit result. (2) fig 46. inverting single-ended circuit for 12-bit adchs input vout vcom r4 r3 r4 + ------------------- - 1 r2 r1 ------ - + ?? ?? ? vin _ pos r2 r1 ------ - ? = 100 mv - 900 mv v com v out 5v 5 v r3 r2 1.24 v r1 r4 r5 vin_pos 0 v - 800 mv (r1 = r2) 0 v - 3.3 v (r1 = 10 x r2) to adchs_n aaa-009655
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 137 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller 13.8.2 non-inverting single-ended circuit with gain = 1 the advantage of having a non-inverting circuit comes at the cost of adding an additional op-amp for a high-impedance voltage reference to prevent the reference level being influenced by the input signal. this circui t is recommended for an input voltage from 100 mv to 800 mv using the internal negative reference voltage. (3) fig 47. non-inverting single -ended circuit with gain = 1 for 12-bit adchs input vout vin _pos vcom (for r3 = r4 and r1 = r2) + = 0 v - 800 mv 100 mv - 900 mv v com vin_pos v out 5 v r4 r3 r1 r7 r6 r5 r2 to adchs_n 1.24 v aaa-009656
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 138 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller 13.8.3 non-inverting single-ended circuit for input 0 v to 3.3 v the advantage of having a non-inverting circuit comes at the cost of adding an additional op-amp for a high-impedance voltage reference to prevent the reference level being influenced by the input signal. this circuit is recommended for an input voltage from 0 v to 3.3 v using the internal negative reference voltage. (4) (5) fig 48. non-inverting single-end ed circuit for input 0 v to 3.3 v for 12-bit adchs input vout vcom r1 r1 r2 + ------------------- - = vcom 1.24 v ?? r3 r3 r4 + ------------------- - = 0 v - 3.3 v 100 mv - 900 mv v com vin_pos v out 5 v r2 r1 r3 r4 to adchs_n 1.24 v aaa-009657
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 139 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller 14. package outline fig 49. package outline lbga256 package references outline version european projection issue date iec jedec mo-192 jeita - - - - - - sot740-2 sot740-2 05-06-16 05-08-04 unit a max mm 1.55 0.45 0.35 1.1 0.9 0.55 0.45 17.2 16.8 17.2 16.8 a 1 dimensions (mm are the original dimensions) lbga256: plastic low profile ball grid array package; 256 balls; body 17 x 17 x 1 mm x a 2 b d e e 1 e 1 15 e 2 15 v 0.25 w 0.1 y 0.12 y 1 0.35 1/2 e 1/2 e a a 2 a 1 detail x d e b a ball a1 index area y y 1 c c ab a b c d e f h k g j l m n p r t 2 4 6 8 10 12 14 16 1 3 5 7 9 11 13 15 ball a1 index area e e e 1 b e 2 c c ? v m ? w m 0 5 10 mm scale
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 140 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller fig 50. package outline of the tfbga100 package references outline version european projection issue date iec jedec jeita sot926-1 - - - - - - - - - sot926-1 05-12-09 05-12-22 unit a max mm 1.2 0.4 0.3 0.8 0.65 0.5 0.4 9.1 8.9 9.1 8.9 a 1 dimensions (mm are the original dimensions) tfbga100: plastic thin fine-pitch ball grid array package; 100 balls; body 9 x 9 x 0.7 mm a 2 b d e e 2 7.2 e 0.8 e 1 7.2 v 0.15 w 0.05 y 0.08 y 1 0.1 0 2.5 5 mm scale b e 2 e 1 e e 1/2 e 1/2 e ac b ? v m c ? w m ball a1 index area a b c d e f h k g j 246810 13579 ball a1 index area b a e d c y c y 1 x detail x a a 1 a 2
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 141 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller 15. soldering fig 51. reflow soldering of the lbga256 package dimensions in mm pslspsrhxhy hx hy sot740-2 solder land plus solder paste occupied area footprint information for reflow soldering of lbga256 package solder land solder paste deposit solder resist p p sl sp sr generic footprint pattern refer to the package outline drawing for actual layout detail x see detail x sot740-2_fr 1.00 0.450 0.450 0.600 17.500 17.500
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 142 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller fig 52. reflow soldering of the tfbga100 package dimensions in mm pslspsrhxhy hx hy sot926-1 solder land plus solder paste occupied area footprint information for reflow soldering of tfbga100 package solder land solder paste deposit solder resist p p sl sp sr generic footprint pattern refer to the package outline drawing for actual layout detail x see detail x sot926-1_fr 0.80 0.330 0.400 0.480 9.400 9.400
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 143 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller 16. abbreviations table 43. abbreviations acronym description adc analog-to-digital converter ahb advanced high-performance bus apb advanced peripheral bus api application programming interface bod brownout detection can controller area network cmac cipher-based message authentication code csma/cd carrier sense multiple access with collision detection dac digital-to-analog converter dc-dc direct current-to-direct current dma direct memory access gpio general purpose input/output irc internal rc irda infrared data association jtag joint test action group lcd liquid crystal display lsb least significant bit mac media access control mcu microcontroller unit miim media independent interface management n.c. not connected ohci open host controller interface otg on-the-go phy physical layer pll phase-locked loop pmc power mode control pwm pulse width modulator rit repetitive interrupt timer rmii reduced media independent interface sdram synchronous dynami c random access memory simd single instruction multiple data spi serial peripheral interface ssi serial synchronous interface ssp synchronous serial port uart universal asynchronous receiver/transmitter ulpi utmi+ low pin interface usart universal synchronous asynchronous receiver/transmitter usb universal serial bus utmi usb2.0 transceiver macrocell interface
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 144 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller 17. references [1] lpc4370 errata sheet.
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 145 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller 18. revision history table 44. revision history document id release date data sheet status change notice supersedes lpc4370 v.2 20131021 product data sheet - lpc4371_70 v.1.1 modifications: ? part lpc4371 removed. ? lcd added to part lpc4370. ? data sheet title changed to lpc4370. ? vadc renamed to adchs throughout the document. pin vadc_neg renamed to adchs_neg. ? otp memory size available for general-purpose use corrected. ? sd/mmc timing parameters corrected. see table 32 . ? band gap characteristics removed. ? description of reset pin updated in table 3 . ? table note 9 added in table 10 . ? minimum value of parameter v dc changed to 0.1 v. see table 34 ? 12-bit adc characteristics ? . ? section 13.8 ? 12-bit adchs input selection ? added. ? table 12 ? peripheral power consumption 12-bit adchs ? added. ? data sheet status changed to product data sheet. lpc4371_70 v.1.1 02112013 objective data sheet - lpc4371_70 v.1 modifications: ? ssp0 boot pin functions corrected in table 5 and table 4. pin p3_3 = ssp0_sck, pin p3_6 = ssp0_ssel, pin p3_7 = ssp0_miso, pin p3_8 = ssp0_mosi. ? section 13.7 ?minimizing interference between digital signals and 12-bit adc signals? added. pin description table updated with table note 13. ? tfbga100 package added. ? table 7 ?limiting values? updated. ? parameter name i dd(adc) changed to i dda in table 10. ? minimum value for parameter v il changed to 0 v in table 10. ? added note to limit data in table 25 ?dynamic characteristics: static asynchronous external memory interface? to single memory accesses. ? table 23 ?dynamic charac teristics: spifi? added. ? power consumption in active mode corrected. see parameter i dd(reg)(3v3) in table 10 and graphs figure 8, figure 9, and figure 10. ? band gap characteristics added. see table 13 and figure 17. ? value of parameter i dd(reg)(3v3) in deep power-down increased to 0.03 a in table 10. ? value of parameter i dd(io) in deep power-down increased to 0.05 a in table 10. ? figure 4 ?ahb multilayer matrix ma ster and slave connections? updated.
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 146 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller modifications: ? parameter i lh (high-level leakage current) for condition v i = 5 v changed to 20 na (max). see table 10. ? parameter v dda(3v3) added for pins usb0_vdda3v3_driver and usb0_vdda3v3 in table 10. ? maximum speed for spi added in section 7.19.3. ? spifi speed changed to 53 mb/s. ? section 7.23.9.1 ?memory retention in power-down modes? added. ? i dd(reg)(3v3) for power-down mode with m0sub sram memory retained added in table 10. ? spi timing data added. see table 22. modifications: ? sgpio timing data added. see table 24. ? spi and sgpio peripheral power consumption added in table 11. ? corrected max voltage on pins usb0_dp, usb0_dm, usb0_vbus, usb1_dp, and usb1_dm in table 7 and table 10 to be consistent with usb specifications. lpc4371_70 v.1 20120808 objective data sheet - lpc43a50_30_20 v.0.5 modifications: ? power consumption data in section 10 ?static characteristics? updated. ? bod levels updated in table 12. ? 12-bit adc characterisation added in table 33. ? pinout corrected for the lbga256 package in table 3: function adchs_3 moved to ball a5 and function adchs_neg moved to ball b5. ? swd removed for ar m cortex-m0 core. table 44. revision history ?continued document id release date data sheet status change notice supersedes
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 147 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller 19. legal information 19.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 19.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 19.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 148 of 150 nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 19.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 20. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
lpc4370 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 21 october 2013 149 of 150 continued >> nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller 21. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 ordering information . . . . . . . . . . . . . . . . . . . . . 5 4.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 5 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 7 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 functional description . . . . . . . . . . . . . . . . . . 57 7.1 architectural overview . . . . . . . . . . . . . . . . . . 57 7.2 arm cortex-m4 processor . . . . . . . . . . . . . . . 57 7.3 arm cortex-m0 processors . . . . . . . . . . . . . . 57 7.3.1 arm cortex-m0 coprocessor . . . . . . . . . . . . . 57 7.3.2 arm cortex-m0 subsytem . . . . . . . . . . . . . . . 57 7.4 interprocessor communicati on . . . . . . . . . . . . 58 7.5 ahb multilayer matrix . . . . . . . . . . . . . . . . . . . 59 7.6 nested vectored interrupt controller (nvic) . 59 7.6.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 7.6.2 interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 60 7.7 system tick timer (systick) . . . . . . . . . . . . . . 60 7.8 event router . . . . . . . . . . . . . . . . . . . . . . . . . . 60 7.9 global input multiplexer array (gima) . . . . . . 61 7.9.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 7.10 system tick timer (systick) . . . . . . . . . . . . . . 61 7.11 on-chip static ram. . . . . . . . . . . . . . . . . . . . . 61 7.12 in-system programming (isp) . . . . . . . . . . . . 61 7.13 boot rom. . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 7.14 memory mapping . . . . . . . . . . . . . . . . . . . . . . 63 7.15 one-time programmable (otp) memory . . . 66 7.16 general purpose i/o (gpio) . . . . . . . . . . . . . 66 7.16.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 7.17 configurable digital peripherals . . . . . . . . . . . 66 7.17.1 state configurable timer (sct) subsystem . . 66 7.17.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.17.2 serial gpio (sgpio) . . . . . . . . . . . . . . . . . . . 67 7.17.2.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.18 ahb peripherals . . . . . . . . . . . . . . . . . . . . . . . 68 7.18.1 general purpose dma (gpdma) . . . . . . . . . . 68 7.18.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 7.18.2 spi flash interface (spifi). . . . . . . . . . . . . . . 68 7.18.2.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.18.3 sd/mmc card interface . . . . . . . . . . . . . . . . . 69 7.18.4 external memory controll er (emc). . . . . . . . . 69 7.18.4.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.18.5 high-speed usb host/device/otg interface (usb0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.18.5.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.18.6 high-speed usb host/device interface with ulpi (usb1) . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.18.6.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.18.7 lcd controller . . . . . . . . . . . . . . . . . . . . . . . . 71 7.18.7.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 7.18.8 ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 7.18.8.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 7.19 digital serial peripherals. . . . . . . . . . . . . . . . . 72 7.19.1 uart1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 7.19.1.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 7.19.2 usart0/2/3 . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7.19.2.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7.19.3 spi serial i/o controller . . . . . . . . . . . . . . . . . 73 7.19.3.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7.19.4 ssp serial i/o controller. . . . . . . . . . . . . . . . . 73 7.19.4.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.19.5 i 2 c-bus interface . . . . . . . . . . . . . . . . . . . . . . 74 7.19.5.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.19.6 i 2 s interface . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.19.6.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.19.7 c_can. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.19.7.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.20 counter/timers and motor control . . . . . . . . . 76 7.20.1 general purpose 32-bit timers/external event counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7.20.1.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7.20.2 motor control pwm . . . . . . . . . . . . . . . . . . . . 76 7.20.3 quadrature encoder inte rface (qei) . . . . . . . 76 7.20.3.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7.20.4 repetitive interrupt (ri) timer. . . . . . . . . . . . . 77 7.20.4.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7.20.5 windowed watchdog ti mer (wwdt) . . . . . . 77 7.20.5.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7.21 analog peripherals . . . . . . . . . . . . . . . . . . . . . 78 7.21.1 12-bit high-speed analog-to-digital converter (adchs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 7.21.1.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 7.21.2 10-bit analog-to-digital converter (adc0/1) . 78 7.21.2.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 7.21.3 digital-to-analog converter (dac). . . . . . . . . 78 7.21.3.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 7.22 peripherals in the rtc power domain . . . . . . 79 7.22.1 rtc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7.22.1.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7.22.2 alarm timer. . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7.23 system control . . . . . . . . . . . . . . . . . . . . . . . . 79 7.23.1 configuration registers (creg) . . . . . . . . . . . 79
nxp semiconductors lpc4370 32-bit arm cortex-m4/m0 microcontroller ? nxp b.v. 2013. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 21 october 2013 document identifier: lpc4370 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 7.23.2 system control unit (scu). . . . . . . . . . . . . . . 79 7.23.3 clock generation unit (cgu) . . . . . . . . . . . . . 80 7.23.4 internal rc oscillator (irc ). . . . . . . . . . . . . . . 80 7.23.5 pll0usb (for usb0) . . . . . . . . . . . . . . . . . . . 80 7.23.6 pll0audio (for audio) . . . . . . . . . . . . . . . . . 80 7.23.7 system pll1 . . . . . . . . . . . . . . . . . . . . . . . . . 80 7.23.8 reset generation unit (rgu). . . . . . . . . . . . . 81 7.23.9 power control . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.23.9.1 memory retention in power-down modes . . . . 82 7.23.9.2 power management controller (pmc) . . . . . . 83 7.24 serial wire debug/jtag. . . . . . . . . . . . . . . . . 84 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 85 9 thermal characteristics . . . . . . . . . . . . . . . . . 86 10 static characteristics. . . . . . . . . . . . . . . . . . . . 87 10.1 power consumption . . . . . . . . . . . . . . . . . . . . 94 10.2 peripheral power consumpt ion . . . . . . . . . . . . 98 10.3 bod static characteristics. . . . . . . . . . . . . . . 100 10.4 electrical pin characteristics . . . . . . . . . . . . . 101 11 dynamic characteristics . . . . . . . . . . . . . . . . 105 11.1 wake-up times . . . . . . . . . . . . . . . . . . . . . . . 105 11.2 external clock for oscillator in slave mode . . 105 11.3 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . 106 11.4 irc oscillator . . . . . . . . . . . . . . . . . . . . . . . . 106 11.5 rtc oscillator . . . . . . . . . . . . . . . . . . . . . . . . 106 11.6 i 2 c-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 11.7 i 2 s-bus interface . . . . . . . . . . . . . . . . . . . . . . 108 11.8 usart interface. . . . . . . . . . . . . . . . . . . . . . 109 11.9 ssp interface . . . . . . . . . . . . . . . . . . . . . . . . 110 11.10 spi interface . . . . . . . . . . . . . . . . . . . . . . . . . 111 11.11 ssp/spi timing diagrams . . . . . . . . . . . . . . . 111 11.12 spifi. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 11.13 sgpio timing . . . . . . . . . . . . . . . . . . . . . . . . 113 11.14 external memory interface . . . . . . . . . . . . . . 115 11.15 usb interface . . . . . . . . . . . . . . . . . . . . . . . 120 11.16 ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 11.17 sd/mmc . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 11.18 lcd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 12 adc/dac electrical characteristics . . . . . . . 124 13 application information. . . . . . . . . . . . . . . . . 128 13.1 lcd panel signal usage . . . . . . . . . . . . . . . . 128 13.2 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . 130 13.3 rtc oscillator . . . . . . . . . . . . . . . . . . . . . . . . 132 13.4 xtal and rtcx prin ted circuit board (pcb) layout guidelines . . . . . . . . . . . . . . . . . . . . . . 132 13.5 standard i/o pin configurat ion . . . . . . . . . . . 132 13.6 reset pin configuration . . . . . . . . . . . . . . . . . 133 13.7 minimizing interference between digital signals and 12-bit adc signals. . . . . . . . . . . 134 13.8 12-bit adchs input selection . . . . . . . . . . . . 134 13.8.1 inverting single-ended circuit . . . . . . . . . . . . 136 13.8.2 non-inverting single-ended circuit with gain = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 13.8.3 non-inverting single-ended circuit for input 0 v to 3.3 v . . . . . . . . . . . . . . . . . . . . . 138 14 package outline. . . . . . . . . . . . . . . . . . . . . . . 139 15 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 16 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . 143 17 references. . . . . . . . . . . . . . . . . . . . . . . . . . . 144 18 revision history . . . . . . . . . . . . . . . . . . . . . . 145 19 legal information . . . . . . . . . . . . . . . . . . . . . 147 19.1 data sheet status . . . . . . . . . . . . . . . . . . . . . 147 19.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . 147 19.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . 147 19.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . 148 20 contact information . . . . . . . . . . . . . . . . . . . 148 21 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

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